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Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
Indian Institute of Science.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Indian Institute of Science.
Nara Institute of Science and Technology.
2010 (English)In: Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI, New York, USA: ACM , 2010, 73-78 p.Conference paper (Refereed)
Abstract [en]

Scan circuit testing generally causes excessive switching activity compared to normal circuit operation. This excessive switching activity causes high peak and average power consumption. Higher peak power causes, supply voltage droop and excessive heat dissipation. This paper proposes a scan cell reordering methodology to minimize the peak power consumption during scan shift operation. The proposed methodology first formulate the problem as graph theoretic problem then solve it by a linear time heuristic. The experimental results show that the methodology is able to reduce up to 48% of peak power in compared to the solution provided by industrial tool.

Place, publisher, year, edition, pages
New York, USA: ACM , 2010. 73-78 p.
National Category
Engineering and Technology
URN: urn:nbn:se:liu:diva-59609DOI: 10.1145/1785481.1785499ISBN: 978-1-4503-0012-4OAI: diva2:352633
20th Great Lakes Symposium on VLSI, GLSVLSI 2010; Providence, RI; United States
Available from: 2010-09-29 Created: 2010-09-21 Last updated: 2014-10-01Bibliographically approved

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Larsson, Erik
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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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ReferencesLink to record
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