Hardware/Software Optimization of Error Detection Implementation for Real-Time Embedded Systems
2010 (English)In: Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2010 IEEE/ACM/IFIP International Conference on, IEEE Operations Center , 2010, 41-50 p.Conference paper (Refereed)
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against transient faults, efficient error detection and recovery techniques have to be employed. Our main focus in this paper is on the efficient implementation of the error detection mechanisms. We have developed techniques to optimize the hardware/software implementation of error detection, in order to minimize the global worst-case schedule length, while meeting the imposed hardware cost constraints and tolerating multiple transient faults. We present two design optimization algorithms which are able to find feasible solutions given a limited amount of resources: the first one assumes that, when implemented in hardware, error detection is deployed on static reconfigurable FPGAs, while the second one considers partial dynamic reconfiguration capabilities of the FPGAs.
Place, publisher, year, edition, pages
IEEE Operations Center , 2010. 41-50 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-59634DOI: 10.1145/1878961.1878970ISBN: 978-1-60558-905-3OAI: oai:DiVA.org:liu-59634DiVA: diva2:352787
International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2010), Scottsdale, AZ, USA, October 24-29, 2010.