liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Analysis and Optimization for Testing Using IEEE P1687
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory.
2010 (English)Independent thesis Advanced level (professional degree), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

 The IEEE P1687 (IJTAG) standard proposal aims at providing a standardized interface between on-chip embedded test, debug and monitoring logic (instruments), such as scan-chains and temperature sensors, and the Test Access Port of IEEE Standard 1149.1 mainly used for board test. A key feature in P1687 is to include Segment Insertion Bits (SIBs) in the scan path. SIBs make it possible to construct a multitude of different P1687 networks for the same set of instruments, and provide flexibility in test scheduling. The work presented in this thesis consists of two parts. In the first part, analysis regarding test application time is given for P1687 networks while making use of two test schedule types, namely concurrent and sequential test scheduling. Furthermore, formulas and novel algorithms are presented to compute the test time for a given P1687 network and a given schedule type. The algorithms are implemented and employed in extensive experiments on realistic industrial designs. In the second part, design of IEEE P1687 networks is studied. Designing the P1687 network that results in the least test application time for a given set of instruments, is a time-consuming task in the absence of automatic design tools. In this thesis work, novel algorithms are presented for automated design of P1687 networks which are optimized with respect to test application time and the required number of SIBs. The algorithms are implemented and demonstrated in experiments on industrial SOCs. 

Place, publisher, year, edition, pages
2010. , 98 p.
Keyword [en]
IEEE P1687, IJTAG, Test Architecures, Test Time Calculation, Design Automation, Test Time Optimization
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-60534ISRN: LIU-IDA/LITH-EX-A--10/040--SEOAI: oai:DiVA.org:liu-60534DiVA: diva2:357396
Presentation
2010-09-29, Alan Turing, Building E, Level 3, Linköping University, 17:15 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2010-10-18 Created: 2010-10-17 Last updated: 2010-10-18Bibliographically approved

Open Access in DiVA

FULLTEXT(5316 kB)506 downloads
File information
File name FULLTEXT01.pdfFile size 5316 kBChecksum SHA-512
129480a2734304a4fbbe223c68ff0309c99595111e430c1775b70db7965085f0e898f7e997c0bd62c95a49e434bf587c0109b626c8e5a50ec29fe65894176174
Type fulltextMimetype application/pdf

Search in DiVA

By author/editor
Ghani Zadegan, Farrokh
By organisation
ESLAB - Embedded Systems Laboratory
Other Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
Total: 506 downloads
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

urn-nbn

Altmetric score

urn-nbn
Total: 791 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf