Reduction in on-resistance of LDMOS transistor for improved RF performance
2009 (English)In: Microelectronics Technology and Devices - SBMicro 2009, Vol. 23, issue 1 / [ed] D. De Lima Monteiro, O. Bonnaud, N. Morimoto, Pennington, New Jersey: The Electrochemical Society , 2009, 413-420 p.Conference paper (Refereed)
In an LDMOS transistor, a low doped drift (LDD) region at the drain side is created to enhance the breakdown voltage (BVDS), but this increases on-resistance (Ron) which degrades the transistor RF performance. In this paper, the LDD region of LDMOS transistor is optimized using two different techniques, (i) a dual implanted-layer p- and n-region in LDD and (ii) an excess interface charge at the RESURF of LDD. Both techniques are used to enhance the carrier density for lower Ron. The comparison revealed that excess interface charge provides 43 % reduction in Ron with BVDS of 70 V, while the dual-implanted region provides 26 % reduction in Ron together with BVDS of 64 - 68 V.
Place, publisher, year, edition, pages
Pennington, New Jersey: The Electrochemical Society , 2009. 413-420 p.
, ECS Transaction, ISSN 1938-6737 (online), 1938-5862 (print)
IdentifiersURN: urn:nbn:se:liu:diva-61592DOI: 10.1149/1.3183746ISBN: 978-1-56677-737-7ISBN: 978-1-60768-087-1OAI: oai:DiVA.org:liu-61592DiVA: diva2:370550
24th Symposium on Microelectronics Technology and Devices, Natal, Brazil