Two-tone PLL for on-chip IP3 test
2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, 3549-3552 p.Conference paper (Refereed)
This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.
Place, publisher, year, edition, pages
IEEE , 2010. 3549-3552 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-61666DOI: 10.1109/ISCAS.2010.5537812ISBN: 978-1-4244-5308-5OAI: oai:DiVA.org:liu-61666DiVA: diva2:370687
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France