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Two-tone PLL for on-chip IP3 test
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, 3549-3552 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

Place, publisher, year, edition, pages
IEEE , 2010. 3549-3552 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-61666DOI: 10.1109/ISCAS.2010.5537812ISBN: 978-1-4244-5308-5 (print)OAI: oai:DiVA.org:liu-61666DiVA: diva2:370687
Conference
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
In thesis
1. Stimuli Generation Techniques for On-Chip Mixed-Signal Test
Open this publication in new window or tab >>Stimuli Generation Techniques for On-Chip Mixed-Signal Test
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2010. 162 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1350
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61712 (URN)978-91-7393-288-2 (ISBN)
Public defence
2010-12-02, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15
Opponent
Supervisors
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17Bibliographically approved

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Ahmad, ShakeelDabrowski, Jerzy

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