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Stimuli Generation Techniques for On-Chip Mixed-Signal Test
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

With increased complexity of the contemporary very large integrated circuits the need for onchip test addressing not only the digital but also analog and mixed-signal RF blocks has emerged. The standard production test has become more costly and the instrumentation is pushed to its limits by the leading edge integrated circuit technologies. Also the chip performance for high frequency operation and the area overhead appear a hindrance in terms of the test access points needed for the instrumentation-based test. To overcome these problems, test implemented on a chip can be used by sharing the available resources such as digital signal processing (DSP) and A/D, D/A converters to constitute a built-in-self-test. In this case, the DSP can serve both as a stimuli generator and response analyzer.

Arbitrary test signals can be achieved using DSP. Specifically, the ΣΔ modulation technique implemented in software is useful to encode a single- or two-tone stimulus as a onebit sequence to generate a spectrally pure signal with a high dynamic range. The sequence can be stored in a cyclic memory on a chip and applied to the circuit under test using a buffer and a simple reconstruction filter. In this way ADC dynamic test for harmonic and intermodulation distortion is carried out in a simple setup. The FFT artifacts are avoided by careful frequency planning for low-pass and band-pass ΣΔ encoding technique. A noise shaping based on a combination of low- and band-pass ΣΔ modulation is also useful providing a high dynamic range for measurements at high frequencies that is a new approach. However, a possible asymmetry between rise and fall time due to CMOS process variations in the driving buffer results in nonlinear distortion and increased noise at low frequencies. A simple iterative predistortion technique is used to reduce the low frequency distortion components by making use of an on-chip DC calibrated ADC that is another contribution of the author.

Some tests, however, like the two-tone RF test that targets linearity performance of a radio receiver, require test stimuli based on a dedicated hardware. For the measurement of the thirdor second-intercept point (IP3/IP2) a spectrally clean stimulus is essential. Specifically, the second- or third-order harmonic or intermodulation products of the stimulus generator should be avoided as they can obscure the test measurement. A challenge in this design is the phase noise performance and spurious tones of the oscillators, and also the distortion-free addition of the two tones. The mutual pulling effect can be minimized by layout isolation techniques.

A new two-tone RF generator based on a specialized phase-locked loop (PLL) architecture is presented as a viable solution for IP3/IP2 on-chip test. The PLL provides control over the frequency spacing of two voltage controlled oscillators. For the two-tone stimulus a highly linear analog  adder is designed to limit distortion which could obscure the IP3 test. A specialized feedback circuit in the PLL is proposed to overcome interference by the reference spurs. The circuit is designed using 65 nm CMOS process. By using a fine spectral resolution the observed noise floor can be reduced to enable the measurement of second- or third-order intermodulation product tones. This also reflects a tradeoff between the test time and the test performance. While the test time to collect the required number of samples can be of milliseconds the number of samples need not be excessive, since the measurements are carried out at the receiver baseband, where the required sampling frequency is relatively low.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2010. , p. 162
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1350
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-61712ISBN: 978-91-7393-288-2 (print)OAI: oai:DiVA.org:liu-61712DiVA, id: diva2:370709
Public defence
2010-12-02, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15
Opponent
Supervisors
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17Bibliographically approved
List of papers
1. ADC on-Chip Dynamic Test by PWM Technique
Open this publication in new window or tab >>ADC on-Chip Dynamic Test by PWM Technique
2008 (English)In: International Conference on Signals and Electronic Systems, IEEE , 2008, p. 15-18Conference paper, Published paper (Refereed)
Abstract [en]

This paper investigates the feasibility of pulse width modulation technique (PWM) for dynamic test of ADCs used for high speed applications. The requirements and limitations of digital PWM signal to noise ratio (SNR) are discussed in terms of pulse-width resolution corresponding to the choice of the carrier- and clock frequency of a pulse-width generator. The PWM SNR response is measured by FFT using coherent sampling for different PWM resolution. Low-pas filtering removing high frequency PWM components is introduced as well to improve PWM SNR and prevent intermodulation effects, which tend to hamper the harmonic distortion test (HD). As an example a 4-bit first-order SigmaDelta ADC under dynamic test is simulated and the requirements for PWM resolution with respect to SNR and HD measurements are identified.

Place, publisher, year, edition, pages
IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-43029 (URN)10.1109/ICSES.2008.4673345 (DOI)70959 (Local ID)78-83-88309-47-2 (ISBN)70959 (Archive number)70959 (OAI)
Conference
International Conference on Signals and Electronic Systems, ICSES '08, 14-17 Sept, Krakow, Poland
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2010-11-17Bibliographically approved
2. On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
Open this publication in new window or tab >>On-chip Stimuli Generation for ADC Dynamic Test by ΣΔ Technique
2009 (English)In: Proceedings in European Conference on Circuit Theory and Design 2009 (ECCTD´09), Antalya, Turkey, IEEE , 2009, p. 105-108Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents application of the ΣΔ modulation technique to the on-chip dynamic test for A/D converters. The wanted stimulus such as a single- or two-tone signal is encoded into one-bit ΣΔ sequence, which after simple low-pass filtering is applied to the circuit under test with low noise and without distortion. In this way a large dynamic range is achieved making the performance harmonic- and intermodulation dynamic test viable. By a systematic approach we select the order and type of a ΣΔ modulator, and develop the frequency plan suitable for spectral measurements on a chip. The technique is illustrated by simulation of a practical ADC under test.

Place, publisher, year, edition, pages
IEEE, 2009
Keyword
Stimuli generation, on-chip test
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-20668 (URN)10.1109/ECCTD.2009.5274977 (DOI)000276473700027 ()978-1-4244-3896-9 (ISBN)
Conference
European Conference on Circuit Theory and Design, ECCTD 2009, 23-27 Aug., Antalya
Note
©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEEAvailable from: 2009-10-13 Created: 2009-09-16 Last updated: 2010-11-17Bibliographically approved
3. Two-tone PLL for on-chip IP3 test
Open this publication in new window or tab >>Two-tone PLL for on-chip IP3 test
2010 (English)In: Proceedings of IEEEInternational Symposium on Circuits and Systems, (ISCAS 10), IEEE , 2010, p. 3549-3552Conference paper, Published paper (Refereed)
Abstract [en]

This paper addresses a built-in-self-test (BiST) to characterize IP3 linearity of a RF receiver front-end. A two-tone stimulus is generated by a phase-lock loop (PLL) in GHz frequency range. The PLL is designed to keep the frequency difference between the two tones under control and in this way to avoid a possible injection-locking. One of the oscillation frequencies and the difference (beat) frequency can be externally controlled. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the VCO and analog adder design. A highly linear analog adder with output referred IP3 of more than +15 dBm is used to generate the RF stimulus. The two-tone power across 50 Ω receiver input impedance can be more than -25 dBm with very low intermodulation distortion of PIM3 = -75 dBc. The receiver performance is not affected significantly by the test set-up. Simulations for linearity and noise performance of the PLL designed in 65nm CMOS show sufficient potential for on-chip IP3 measurements in the GHz frequency range.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61666 (URN)10.1109/ISCAS.2010.5537812 (DOI)978-1-4244-5308-5 (ISBN)
Conference
Proceedings of 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30-June, Paris, France
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
4. Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
Open this publication in new window or tab >>Cancellation of Spurious Spectral Components in One-Bit Stimuli Generator
2010 (English)In: Proceedings of IEEEInternational Conference on Signals and Electronic Systems, (ICSES 10) / [ed] Andrzej Pułka and Tomasz Golonek, IEEE , 2010, p. 393-396Conference paper, Published paper (Refereed)
Abstract [en]

This work presents a cancellation technique of non-linear distortion components of one-bit digital stimulus sequence which is generated in software by a ΣΔ modulator. The stimulus is stored in a cyclic memory and applied to a circuit under test through a driving buffer and a simple lowpass reconstruction filter. The distortion components originate from buffer imperfections which result in a possible asymmetry between rising and falling edges of a NRTZ waveform representing the encoded stimulus. We show that the distortion components can be cancelled by using a simple predistortion technique. In addition an on-chip DC-calibrated ADC can be used to identify the second-order nonlinear products of the driving buffer. This procedure allows for cancellation of all the second-order distortions before the actual test and it can be extended to the third order terms as well.

Place, publisher, year, edition, pages
IEEE, 2010
National Category
Signal Processing
Identifiers
urn:nbn:se:liu:diva-61668 (URN)978-1-4244-5307-8 (ISBN)
Conference
International Conference on Signals and Electronic Systems (ICSES), 7-10 Sept, Gliwice, Poland
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2015-09-14Bibliographically approved
5. Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
Open this publication in new window or tab >>Design of Two-Tone RFGenerator for On-Chip IP3/IP2 Test
(English)Manuscript (preprint) (Other academic)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61669 (URN)
Conference
IEEE Transactions on Circuits and Systems–II
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2010-11-17
6. One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
Open this publication in new window or tab >>One-bit ΣΔ Encoded StimulusGeneration for on-Chip ADC Test
2010 (English)In: Journal of electronic testing, ISSN 0923-8174, E-ISSN 1573-0727Article in journal (Other academic) Submitted
Place, publisher, year, edition, pages
Springer, 2010
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-61687 (URN)
Available from: 2010-11-17 Created: 2010-11-17 Last updated: 2017-12-12Bibliographically approved

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Ahmad, Shakeel

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