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Design Space Exploration of Instruction Set Customizable MPSoCs for Multimedia Applications
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Institute of High Performance, Singapore.
National University of Singapore.
Technical University of Munich, Germany.
2010 (English)In: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2010), IEEE , 2010Conference paper, Published paper (Refereed)
Abstract [en]

Multiprocessor System-on-Chips or MPSoCs in the embedded systems domain are increasingly employing multiple customizable processor cores. Such cores offer higher performance through application-specific instruction-set extensions without sacrificing the flexibility of software solutions. Existing techniques for generating appropriate custom instructions for an application domain are primarily restricted to specializing a single processor with the objective of maximizing performance. In a customizable MPSoC, in contrast, the different processor cores have to be customized in a synergistic fashion to create a heterogeneous MPSoC solution that best suits the application. Moreover, such a platform presents conflicting design tradeoffs between system throughput and on-chip memory/logic capacity. In this paper, we propose a framework to systematically explore the complex design space of customizable MPSoC platforms. In particular, we focus on multimedia streaming applications, as this class of applications constitutes a primary target of MPSoC platforms. We capture the high variability in execution times and the bursty nature of streaming applications through appropriate mathematical models. Thus, our framework can efficiently and accurately evaluate the different customization choices without resorting to expensive system-level simulations. We perform a detailed case study of an MPEG encoder application with our framework. It reveals design points with interesting tradeoffs between silicon area requirement for the custom instructions and the on-chip storage for partially-processed video data, while ensuring that all the design points strictly satisfy required QoS guarantees.

Place, publisher, year, edition, pages
IEEE , 2010.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-63299DOI: 10.1109/ICSAMOS.2010.5642070ISBN: 978-1-4244-7936-8 (print)ISBN: 978-1-4244-7938-2 (print)OAI: oai:DiVA.org:liu-63299DiVA: diva2:377961
Conference
SAMOS 2010
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2013-09-20

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Bordoloi, Unmesh D.

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CiteExportLink to record
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf