Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010 (English)In: Design and Test Technology for Dependable Systems-on-chip / [ed] Raimund Ubar, Jaan Raik, Heinrich Theodor Vierhaus, Information Science Publishing , 2010, 578- p.Chapter in book (Other academic)
Designing reliable and dependable embedded systems has become increasingly important as the failure of these systems in an automotive, aerospace or nuclear application can have serious consequences.
Design and Test Technology for Dependable Systems-on-Chip covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). This book provides insight into refined "classical" design and test topics and solutions for IC test technology and fault-tolerant systems.
Place, publisher, year, edition, pages
Information Science Publishing , 2010. 578- p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-63306ISBN: 160-9602-12-9ISBN: 978-1609-6021-2-3OAI: oai:DiVA.org:liu-63306DiVA: diva2:378001