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Power Constrained Test Scheduling for 3D Stacked Chips: (poster)
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2010 (English)In: 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits, Austin, TX, USA., 2010Conference paper, Poster (with or without abstract) (Refereed)
Place, publisher, year, edition, pages
2010.
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Engineering and Technology
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URN: urn:nbn:se:liu:diva-63308OAI: oai:DiVA.org:liu-63308DiVA: diva2:378007
Conference
3DTEST 2010
Available from: 2010-12-15 Created: 2010-12-15 Last updated: 2017-03-20

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SenGupta, BreetaIngelsson, UrbanLarsson, Erik

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SenGupta, BreetaIngelsson, UrbanLarsson, Erik
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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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  • Other style
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Output format
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