Design Automation for IEEE P1687
2011 (English)In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE , 2011, 1-6 p.Conference paper (Refereed)
The IEEE P1687 (IJTAG) standard proposal aimsat standardizing the access to embedded test and debug logic(instruments) via the JTAG TAP. P1687 specifies a componentcalled Segment Insertion Bit (SIB) which makes it possible toconstruct a multitude of alternative P1687 instrument accessnetworks for a given set of instruments. Finding the best accessnetwork with respect to instrument access time and the numberof SIBs is a time-consuming task in the absence of EDA support.This paper is the first to describe a P1687 design automationtool which constructs and optimizes P1687 networks. Our EDAtool, called PACT, considers the concurrent and sequential accessschedule types, and is demonstrated in experiments on industrialSOCs, reporting total access time and average access time.
Place, publisher, year, edition, pages
IEEE , 2011. 1-6 p.
, Design, automation and test in Europe, ISSN 1530-1591
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-63309DOI: 10.1109/DATE.2011.5763228ISBN: 978-1-61284-208-0OAI: oai:DiVA.org:liu-63309DiVA: diva2:378011
14th Design, Automation and Test in Europe Conference and Exhibition, DATE 2011; Grenoble; France