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ASIP for Wireless Communication and Media
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2010 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

While general purpose processors reach both high performance and high application flexibility, this comes at a high cost in terms of silicon area and power consumption. In systems where high application flexibility is not required, it is possible to trade off flexibility for lower cost by tailoring the processor to the application to create an Application Specific Instruction set Processor (ASIP) with high performance yet low silicon cost.

This thesis demonstrates how ASIPs with application specific data types can provide efficient solutions with lower cost. Two examples are presented, an audio decoder ASIP for audio and music processing and a matrix manipulation ASIP for MIMO radio baseband signal processing.

The audio decoder ASIP uses a 16-bit floating point data type to reduce the size of the data memory to about 60% of other solutions that use a 32-bit data type. Since the data memory occupies a major part of the silicon area, this has a significant impact on the total silicon area, and thereby also the static and dynamic power consumption. The data width reduction can be done without any noticeable artifacts in the decoded audio due to the natural masking effect ofthe human ear.

The matrix manipulation SIMD ASIP is designed to perform various matrix operations such as matrix inversion and QR decomposition of small complex-valued matrices. This type of processing is found in MIMO radio baseband signal processing and the matrices are typically not larger than 4x4. There have been solutions published that use arrays of fixed-function processing elements to perform these operations, but the proposed ASIP performs the computations in less time and with lower hardware cost.

The matrix manipulation ASIP data path uses a floating point data type to avoid data scaling issues associated with fixed point computations, especially those related to division and reciprocal calculations, and it also simplifies the program control flow since no special cases for certain inputs are needed which is especially important for SIMD architectures.

These two applications were chosen to show how ASIPs can be a suitable alternative and match the requirements for different types of applications, to provide enough flexibility and performance to support different standards and algorithms with low hardware cost.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2010. , 43 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1298
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-65355ISBN: 978-91-7393-450-3 (print)OAI: oai:DiVA.org:liu-65355DiVA: diva2:395174
Public defence
2010-02-26, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (English)
Opponent
Supervisors
Available from: 2011-02-04 Created: 2011-02-04 Last updated: 2011-02-04Bibliographically approved
List of papers
1. Using low precision floating point numbers to reduce memory cost for MP3 decoding
Open this publication in new window or tab >>Using low precision floating point numbers to reduce memory cost for MP3 decoding
2004 (English)In: International Workshop on Multimedia Signal Processing, IEEE Xplore , 2004, 119-122 p.Conference paper, Published paper (Refereed)
Abstract [en]

The purpose of our work has been to evaluate the practicality of using a 16-bit floating point representation to store the intermediate sample values and other data in memory during the decoding of MP3 bit streams. A floating point number representation offers a better trade-off between dynamic range and precision than a fixed point representation for a given word length. Using a floating point representation means that smaller memories can be used which leads to smaller chip area and lower power consumption without reducing sound quality. We have designed and implemented a DSP processor based on 16-bit floating point intermediate storage. The DSP processor is capable of decoding all MP3 bit streams at 20 MHz and this has been demonstrated on an FPGA prototype.

Place, publisher, year, edition, pages
IEEE Xplore, 2004
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-16559 (URN)10.1109/MMSP.2004.1436435 (DOI)0-7803-8578-0 (ISBN)
Available from: 2009-02-02 Created: 2009-02-02 Last updated: 2015-02-18Bibliographically approved
2. Efficient Complex Matrix Inversion for MIMO Software Defined Radio
Open this publication in new window or tab >>Efficient Complex Matrix Inversion for MIMO Software Defined Radio
2007 (English)In: International Symposium on Circuits and Systems, ISCAS,2007, IEEE , 2007, 2610-2613 p.Conference paper, Published paper (Refereed)
Abstract [en]

Complex matrix inversion is a very computationally demanding operation in advanced multi-antenna wireless communications. Traditionally, systolic array-based QR decomposition (QRD) is used to invert large matrices. However, the matrices involved in MIMO baseband processing in mobile handsets are generally small which means QRD is not necessarily efficient. In this paper, a new method is proposed using programmable hardware units which not only achieves higher performance but also consumes less silicon area. Furthermore, the hardware can be reused for many other operations such as complex matrix multiplication, filtering, correlation and FFT/IFFT.

Place, publisher, year, edition, pages
IEEE, 2007
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-39855 (URN)10.1109/ISCAS.2007.377850 (DOI)51537 (Local ID)1-4244-0920-9 (ISBN)51537 (Archive number)51537 (OAI)
Conference
nternational Symposium on Circuits and Systems (ISCAS 2007), 27-20 May, New Orleans, Louisiana, USA
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04
3. Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding
Open this publication in new window or tab >>Complexity Reduction of Matrix Manipulation for Multi-User STBC-MIMO Decoding
Show others...
2007 (English)In: IEEE Sarnoff Symmposium,2007, 2007, 1-5 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions significantly reduce the number of operations which makes them more than 4 times faster than several other solutions in the literature. Furthermore, compared to fixed function VLSI implementations, our solution is more flexible and consumes less silicon area because the hardware is programmable and it can be reused for many other operations such as filtering, correlation and FFT/IFFT. Besides the analysis of the general computational complexity based on the number of basic operations, the computational latency is also measured in clock cycles based on the conceptual hardware for real-time matrix manipulations.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-39861 (URN)10.1109/SARNOF.2007.4567354 (DOI)51543 (Local ID)978-1-4244-2483-2 (ISBN)51543 (Archive number)51543 (OAI)
Conference
Sarnoff Symposium, April 30-May 2, Nassau Inn, Princeton, NJ, USA
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04
4. Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM
Open this publication in new window or tab >>Implementation of a Programmable Linear MMSE Detector for MIMO-OFDM
2008 (English)In: IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP,2008, IEEE , 2008, 5396-5399 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a linear minimum mean square error (LMMSE) symbol detector for MIMO-OFDM enabled mobile terminals. The detector is implemented using a programmable baseband processor aimed for software-defined radio (SDR). Owing to the dynamic range supplied by the floating-point SIMD datapath, special algorithms can be adopted to reduce the computational latency of detection. The programmable solution not only supports different transmit/receive antenna configurations, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional solutions, the one proposed in this paper is smaller, more flexible and faster.

Place, publisher, year, edition, pages
IEEE, 2008
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-42734 (URN)10.1109/ICASSP.2008.4518880 (DOI)68460 (Local ID)978-1-4244-1483-3 (ISBN)68460 (Archive number)68460 (OAI)
Conference
IEEE International Conference on Acoustics, Speech and Signal Processing, March 31-April 4, Las Vegas, NV, USA
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04Bibliographically approved
5. Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor
Open this publication in new window or tab >>Real-Time Alamouti STBC Decoding on A Programmable Baseband Processor
2008 (English)Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a space-time block coding decoder for MIMO-OFDM enabled mobile terminals. The decoder is implemented using a programmable baseband processor aimed for software-defined radio (SDR). The dynamic range supplied by the floating-point SIMD datapath allows special algorithms to significantly reduce the computational latency of decoding. The programmable solution not only supports different transmit/receive antenna configuration, but also allows hardware multiplexing to obtain silicon and power efficiency. Compared to several existing fixed-functional ASIC solutions in literature, the one proposed in this paper is by far the smallest, fastest and with more flexibility.

National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-42763 (URN)10.1109/ICCSC.2008.65 (DOI)68620 (Local ID)978-1-4244-1707-0 (ISBN)68620 (Archive number)68620 (OAI)
Conference
4th IEEE International Conference on Circuits and Systems for Communications, 26-28 May, Shanghai, China
Available from: 2009-10-10 Created: 2009-10-10 Last updated: 2011-02-04Bibliographically approved

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