A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
2010 (English)In: Proceedings of the ESSCIRC, 2010, Seville: IEEE , 2010, 310-313 p.Conference paper (Refereed)
This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.
Place, publisher, year, edition, pages
Seville: IEEE , 2010. 310-313 p.
, ESSCIRC, ISSN 1930-8833 ; 2010
CMOS integrated circuits, code division multiple access, harmonic distortion, invertors, linearisation techniques, phase shift keying, power amplifiers, radiofrequency amplifiers, short-circuit currents
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65459DOI: 10.1109/ESSCIRC.2010.5619706ISBN: 978-1-4244-6662-7OAI: oai:DiVA.org:liu-65459DiVA: diva2:395831
36th European Solid State Circuits Conference (ESSCIRC), 14-16 September, Seville, Spain