On-chip test for RF IC transceivers
2010 (English)In: European Microwave Week Workshop, 2010, 16-30 p.Conference paper (Refereed)
Over the years, production test of digital ICs has reached a significant degree of maturity. This progress has been enabled by several techniques, such as fault simulation, test-pattern generation and the built-in-self-test (BiST). Unlike this, much less success has been achieved in the analog/RF and mixed-signal ICs domain, where functional testing has been widely used and the major advances have been in the capabilities of expensive automatic test equipment (ATE). At present, the advancing complexity and performance of mixed-signal and RF ICs are pushing functional test methods and the ATE to the edge of their limits. In this context, alternative approaches based on analog fault modeling, design for testability (DfT), and BiST, so far not appreciated by industry, can largely alleviate the problem and cut the test costs.In this tutorial the essentials of the on-chip test for IC RF transceivers will be presented. The available on chip baseband DSP can serve as a tester while the RF front-end is reconfigured for test. The basic test setup is a loopback, enabled by a test attenuator and in some cases by an offset mixer, too. Different variants of this setup adopt the bypassing technique to boost testability. Also the observability blocks (RF detectors) can be incorporated. The existing limitations and tradeoffs in terms of test feasibility, controllability and observability versus the chip performance will be discussed. The fault-oriented approach and the sensitization techniques will be emphasized. Implementation examples in CMOS technology will be included as well.
Place, publisher, year, edition, pages
2010. 16-30 p.
RF test, DfT, BiST, Loopback test
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65472OAI: oai:DiVA.org:liu-65472DiVA: diva2:395862