A multi-segment clocking scheme to reduce on-chip EMI
2011 (English)In: IEEE International SoC Conference (SoCC), Taipei, Taiwan: IEEE , 2011, 251-255 p.Conference paper (Refereed)
This paper presents an EMI reduction technique for VLSI circuits in which a multi-segment clock is employed. It is proven that utilizing a clock signal with relaxed edge rate can suppress the harmonic tones at the output spectrum. However, it calls for higher short-circuit power dissipation in the clocked devices. Proposed multi-segment clock signal reduces the electromagnetic radiations while keeping the short circuit power dissipation in an acceptable level. Simulation results in 65-nm CMOS process are presented to prove the capability of such a clock network in EMI reduction.
Place, publisher, year, edition, pages
Taipei, Taiwan: IEEE , 2011. 251-255 p.
EMI, clock, clock distribution, short circuit power, CMOS
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65492DOI: 10.1109/SOCC.2011.6085110OAI: oai:DiVA.org:liu-65492DiVA: diva2:395945