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Redundancy reduction for high-speed FIR filter architectures based on carry-save adder trees
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.ORCID iD: 0000-0003-3470-3911
2010 (English)In: International Symposium on Circuits and Systems, IEEE , 2010Conference paper, Published paper (Refereed)
Abstract [en]

In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.

Place, publisher, year, edition, pages
IEEE , 2010.
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-65501DOI: 10.1109/ISCAS.2010.5537997OAI: oai:DiVA.org:liu-65501DiVA: diva2:396026
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2015-03-11

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Blad, AntonGustafsson, Oscar

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  • apa
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