Redundancy reduction for high-speed FIR filter architectures based on carry-save adder trees
2010 (English)In: International Symposium on Circuits and Systems, IEEE , 2010Conference paper (Refereed)
In this work we consider high-speed FIR filter architectures implemented using, possibly pipelined, carry-save adder trees for accumulating the partial products. In particular we focus on the mapping between partial products and full adders and propose a technique to reduce the number of carry-save adders based on the inherent redundancy of the partial products. The redundancy reduction is performed on the bit-level to also work for short wordlength data such as those obtained from sigma-delta modulators.
Place, publisher, year, edition, pages
IEEE , 2010.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-65501DOI: 10.1109/ISCAS.2010.5537997OAI: oai:DiVA.org:liu-65501DiVA: diva2:396026