Rate-compatible LDPC code decoder using check-node merging
2010 (English)In: Proceedings of Asilomar Conference on Signals, Systems and Computers, IEEE , 2010, 1119-1123 p.Conference paper (Refereed)
The use of rate-compatible error correcting codes offers several advantages as compared to the use of fixed-rate codes: a smooth adaptation to the channel conditions, the possibility of incremental Hybrid ARQ schemes, as well as sharing of the encoder and decoder implementations between the codes of different rates. In this paper, the implementation of a decoder for rate-compatible quasi-cyclic LDPC codes is considered. Assuming the use of a code ensemble obtained through puncturing of a low-rate mother code, the decoder achieves significantly reduced convergence rates by merging the check node neighbours of the punctured variable nodes. The architecture uses the min-sum algorithm with serial node processing elements to efficiently handle the wide spread of node degrees that results from the merging of the check nodes.
Place, publisher, year, edition, pages
IEEE , 2010. 1119-1123 p.
National CategoryOther Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-65508DOI: 10.1109/ACSSC.2010.5757578ISBN: 978-1-4244-9722-5OAI: oai:DiVA.org:liu-65508DiVA: diva2:396049
44th Asilomar Conference on Signals, Systems and Computers, Asilomar 2010; Pacific Grove, CA; United States