IP2 calibration of ADC for SDR receiver
2010 (English)In: International Conference on Signals and Electronic Systems, Gliwice, Poland: IEEE , 2010, 233-236 p.Conference paper (Refereed)
In this paper we discuss a possible variant of A/D conversion in pure software-defined radio (SDR) receiver architecture. The requirements for the ADC dynamic range and linearity are formulated for the contemporary personal and data-communication RF standards. A technique for IP2 calibration of a ΣΔ ADC designed in 65 nm CMOS is introduced. The ADC is a lowpass second order ΣΔ modulator with one bit quantizer. It works as a zero-IF/ low-IF downconverter using a clock frequency upto 3 GHz. In simulation the proposed ADC meets the requirements for most of the popular RF standards such as E-GSM, LTE and WLAN. The dynamic range of 70-100 dB, IIP3 > 22dBm, and IIP2 > 70dBm (after calibration) are demonstrated.
Place, publisher, year, edition, pages
Gliwice, Poland: IEEE , 2010. 233-236 p.
CMOS integrated circuits, radio receivers, sigma-delta modulation, software radio
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65524ISBN: 978-1-4244-5307-8OAI: oai:DiVA.org:liu-65524DiVA: diva2:396390