Analysis of Twiddle Factor Memory Complexity of Radix-2^i Pipelined FFTs
2009 (English)In: Conference Record - Asilomar Conference on Signals, Systems and Computers, IEEE , 2009, 217-220 p.Conference paper (Refereed)
In this work, we analyze different approaches to store the coefficient twiddle factors for different stages of pipelined Fast Fourier Transforms (FFTs). The analysis is based on complexity comparisons of different algorithms when implemented on Field-Programmable Gate Arrays (FPGAs) and ASIC for different radix-2^i algorithms. The objective of this work is to investigate the best possible combination for storing the coefficient twiddle factor for each stage of the pipelined FFT.
Place, publisher, year, edition, pages
IEEE , 2009. 217-220 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-65855DOI: 10.1109/ACSSC.2009.5470121ISBN: 978-1-4244-5825-7OAI: oai:DiVA.org:liu-65855DiVA: diva2:399584
43rd Asilomar Conference on Signals, Systems and Computers; Pacific Grove, CA; United States
©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Fahad Qureshi and Oscar Gustafsson, Analysis of Twiddle Factor Memory Complexity of Radix-2^i Pipelined FFTs, 2009, 43rd Asilomar Conference on Signals, Systems, and Computers, 217-220.2011-02-242011-02-222015-03-11Bibliographically approved