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SoC-Level Fault Management based on P1687 IJTAG
Ericsson, Linköping, Sweden.
(Testonica Lab, Estonia)
Linköping University, Department of Computer and Information Science, ESLAB - Embedded Systems Laboratory. Linköping University, The Institute of Technology.
2011 (English)Other (Other academic)
Abstract [en]

Fault tolerance and fault management mechanisms are necessary means to reduce the impact of soft errors and wear out in electronic devices. The semiconductor products manufactured with latest and emerging processes are increasingly affected by these effects. The presentation describes a new general scalable fault management architecture based on the latest upcoming DFT standard IEEE P1687 IJTAG. The standard allows to create an efficient and regular network for handling fault detection information, manage test and system resources as a system-wide background process during system operation.

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Engineering and Technology
URN: urn:nbn:se:liu:diva-67574OAI: diva2:411369
Event: Thu Mar 17, 2011: DIAMOND tutorial at DATE'11: Handling the challenges of debugging and reliability. At: Design, Automation and Test in Europe (DATE 2011), Grenoble, France, March 14-18, 2011.Available from: 2011-04-18 Created: 2011-04-18 Last updated: 2011-05-05

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Larsson, Erik
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ESLAB - Embedded Systems LaboratoryThe Institute of Technology
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