A 2.4 GS/s, Single-channel, 31.3 dB SNDR at Nyquist, 8-bit Pipeline ADC in 65nm CMOS
2011 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 46, no 7, 1575-1584 p.Article in journal (Refereed) Published
This paper presents a high-speed single-channel pipeline analog-to-digital converter sampling at 2.4 GS/s. The high sample-rate is achieved through the use of fast openloop current-mode amplifiers and the early comparison scheme. The bounds on the sub-ADC sampling instance are analyzed based on sufficient settling for a decision as well as metastability. Implemented in a 65nm general purpose CMOS technology the SNDR is above 30.1 dB in the Nyquist band, being 34.1 and 31.3 dB at low frequency and Nyquist, respectively. This shows that multi-GS/s pipeline ADCs are feasible as key building blocks in interleaved structures.
Place, publisher, year, edition, pages
IEEE , 2011. Vol. 46, no 7, 1575-1584 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-67622DOI: 10.1109/JSSC.2011.2143811ISI: 000292102400007OAI: oai:DiVA.org:liu-67622DiVA: diva2:411994