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A 7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOS
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
(English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper presents a pipeline analog-to-digital converter achieving 7.5 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used and by individually biasing the pMOS and nMOS, symmetrical layout as well as transconductance can be achieved, resulting in increased closed-loop linearity and a THD of -52 dB. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary weighted capacitors, which removes the need for digital background calibration. With a power dissipation of 73 mW and an FoM of 0.4 pJ/conv-step, high sample-rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency.

National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-67623OAI: oai:DiVA.org:liu-67623DiVA: diva2:411996
Available from: 2011-04-20 Created: 2011-04-20 Last updated: 2011-04-20Bibliographically approved
In thesis
1. Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components
Open this publication in new window or tab >>Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The scaling of CMOS technologies has increased the performance of general purpose processors and DSPs. However, analog circuits designed in the same process have not been able to utilize the scaling to the same extent, suffering from reduced voltage headroom and reduced analog gain. Integration of the system components on the same die means that the analog-to-digital converters (ADCs) needs to be implemented in the newest technologies in order to utilize the digital capabilities at these process nodes. To design efficient ADCs in nanoscale CMOS technologies, there is a need to both understand the physical limitations as well as to develop new architectures and circuits that take full advantage of the potential that process has to offer.

As the technology scales to smaller feature sizes, the possible sample-rate of ADCs can be increased. This thesis explores the design of high-speed ADCs and investigates architectural and circuit concepts that address the problems associated with lower supply voltage and analog gain. The power dissipation of Nyquist rate ADCs is investigated and lower bounds, as set by both thermal noise and minimum feature sizes are formulated. Utilizing the increasing digital performance, low-accuracy analog components can be used, assisted by digital correction or calibration, which leads to a reduction in power dissipation. Through the aid of new techniques and concepts, the power dissipation of low-to-medium resolution ADCs benefit from going to more modern CMOS processes, which is supported by both theory and published results.

New architectures and circuits of high-speed ADCs are explored in test-chips based on the flash and pipeline ADC architectures. Two flash ADCs were developed, both based on a new comparator that suppresses common-mode kick-back by a factor of 6x compared to conventional topologies. The first flash ADC is based on redundancy in the comparator array, allowing the use of low-accuracy, small-sized and low-power comparators to achieve an overall low-power solution. The flash ADC achieves 4.0 effective bits at 2.5 GS/s while dissipating 30 mW of power. The second Flash ADC further explores the use of low-accuracy components, relying on the process variations to generate the reference levels based on the mismatch induced comparator offsets. The reference-free ADC achieves a resolution of 3.7 bits at 1.5 GS/s and dissipates 23 mW of power, showing that process variations does not necessarily has to be seen as detrimental to circuit performance, but rather can be seen as a source of diversity.

In two implemented pipeline ADCs, the potential of very high sample-rates and energy efficiency is explored. The first pipeline ADC utilizes a new high-speed currentmode amplifier in open-loop configuration in order to reach a sample-rate of 2.4 GS/s in a single-channel pipeline ADC, a speed which is significantly faster than previous stateof-the-art The ADC achieved above 4.7 bits throughout the Nyquist range while dissipating 318 mW. The second pipeline ADC relies on an inverter-based amplifier, used in switched-capacitor feedback in order to keep the amplifier biased at a poweroptimal point. The amplifier uses asymmetrically biased transistors in order to better match the p- and n-type transistors, which increases linearity and allows for fully symmetrical layout. Operating at 1.0 GS/s, the effective resolution of the ADC was 7.5 bits and the power dissipation was 73 mW. This shows that it is possible to achieve low power dissipation while maintaining both high sample-rates and medium resolution.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press, 2011. 61 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1367
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-67624 (URN)978-91-7393-203-5 (ISBN)
Public defence
2011-05-20, Visionen, Hus B, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2011-04-20 Created: 2011-04-20 Last updated: 2011-04-27Bibliographically approved

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Sundström, TimmySvensson, ChristerAlvandpour, Atila

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