A 7.5 ENOB, 1.0 GS/s, 73 mW Pipeline ADC in 65nm CMOS
(English)Manuscript (preprint) (Other academic)
This paper presents a pipeline analog-to-digital converter achieving 7.5 ENOB at 1.0 GS/s. A single-stage inverter-based amplifier is used and by individually biasing the pMOS and nMOS, symmetrical layout as well as transconductance can be achieved, resulting in increased closed-loop linearity and a THD of -52 dB. With the amplifier in a switched-capacitor configuration, the optimal bias point can be maintained throughout the input range, which minimizes the power overhead of the MDAC. Calibration of the stage gain is digitally controlled through binary weighted capacitors, which removes the need for digital background calibration. With a power dissipation of 73 mW and an FoM of 0.4 pJ/conv-step, high sample-rate is achieved in a medium resolution pipeline ADC without compromising the energy efficiency.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-67623OAI: oai:DiVA.org:liu-67623DiVA: diva2:411996