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Understanding Sub-threshold source coupled logic for ultra-low power application
Linköping University, Department of Electrical Engineering, Electronics System.
Linköping University, Department of Electrical Engineering, Electronics System.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

This thesis work primarily focuses on the applicability of sub-threshold source coupled logic (STSCL) for building digital circuits and systems that run at very low voltage and promise to provide desirable performance with excellent energy savings. Sectors like bio-engineering and smart sensors require the energy consumption to be effectively very low for long battery life. Alongside meeting the ultra-low power specification, the system must also be reliable, robust, and perform well under harsh conditions. In this thesis work, logic gates are designed and analyzed, using STSCL. These gates are further used for implementation of digital subsystems in small-sized smart dust sensors which would operate at very low supply voltages and consume extremely low power.

For understanding the performance of STSCL with respect to ultra-low power and energy; a seven-stage ring oscillator, a 4-by-4 array multiplier, a fifth-order FIR filter and finally a fifty-fifth-order FIR filter were designed. The subcircuits and systems have been simulated for different supply voltages, scaling down to 0.2 V, at different temperature values (-20oC and 70oC) in both 45 nm and 65 nm process technologies. The chosen architectures for the FIR filters and array multiplier were conventional and essentially taken from traditional CMOS-based designs.

The simulated results are studied, analyzed and compared with same CMOS-based digital circuits. The results show on the advantage of STSCL-based digital systems over CMOS. Simulation results provide an energy consumption of 1.1388 nJ for a fifty-fifth-order FIR filter, at low temperatures (-20oC), using STSCL logic, which is comparatively less than for the corresponding CMOS logic implementation.

Place, publisher, year, edition, pages
2011. , 82 p.
Keyword [en]
STSCL, CMOS-CVL, SCL, PDP, NCL, DFF, FIR, slew rate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-69404ISRN: LITH-ISY-EX--11/4465--SEOAI: oai:DiVA.org:liu-69404DiVA: diva2:427041
Subject / course
Electronics Systems
Presentation
2011-05-24, Nollstället, Linköping University, Linköping, 10:15 (English)
Uppsok
Technology
Supervisors
Examiners
Available from: 2011-06-27 Created: 2011-06-27 Last updated: 2011-06-27Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
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  • vancouver
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  • de-DE
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  • Other locale
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Output format
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  • asciidoc
  • rtf