Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011 (English)In: The 11th Swedish System-on-Chip Conference, Varberg, Sweden, May 2-3, 2011, 2011Conference paper (Other academic)
In this paper we have proposed a test cost model for core-based 3D Stacked ICs (SICs) connected by Through Silicon Vias (TSVs). Unlike in the case of non-stacked chips, where the test flow is well defined by applying the same test schedule both at wafer sort and at package test, the most cost-efficient test flow for 3D TSV-SICs is yet undefined. Therefore, analysing the various alternatives of test flow, we present a cost model with the optimal test flow. In the test flow alternatives, we analyse the effect of all possible moments of testing for a 3D TSV-SIC, viz., wafer sort, intermediate test and package test. For the optimal test flow, we have performed experiments with various varying yield and test time parameters, which further support our claim.
Place, publisher, year, edition, pages
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-69731OAI: oai:DiVA.org:liu-69731DiVA: diva2:432221