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Implementing FFT-based Digital Channelized Receivers on FPGA Platforms
Universidad Politecnica de Madrid, Madrid, Spain.
Universidad Politecnica de Madrid, Madrid, Spain.
Universidad Politecnica de Madrid, Madrid, Spain.
Universidad Politecnica de Madrid, Madrid, Spain.
2008 (English)In: IEEE Transactions on Aerospace and Electronic Systems, ISSN 0018-9251, E-ISSN 1557-9603, Vol. 44, no 4, 1567-1585 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents an in-depth study of the implementationand characterization of fast Fourier transform (FFT) pipelinedarchitectures suitable for broadband digital channelized receivers.When implementing the FFT algorithm on field-programmablegate array (FPGA) platforms, the primary goal is to maximizethroughput and minimize area. Feedback and feedforwardarchitectures have been analyzed regarding key designparameters: radix, bitwidth, number of points and stage scaling.Moreover, a simplification of the FFT algorithm, the monobitFFT, has been implemented in order to achieve faster real timeperformance in broadband digital receivers. The influence ofthe hardware implementation on the performance of digitalchannelized receivers has been analyzed in depth, revealinginteresting implementation trade-offs which should be taken intoaccount when designing this kind of signal processing systems onFPGA platforms.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2008. Vol. 44, no 4, 1567-1585 p.
Keyword [en]
Fast Fourier Transform (FFT), Pipelined Architecture, Very-large-scale integration (VLSI), Channelized Receiver, FPGA
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-70359DOI: 10.1109/TAES.2008.4667732OAI: oai:DiVA.org:liu-70359DiVA: diva2:438512
Available from: 2011-09-02 Created: 2011-09-02 Last updated: 2017-05-30Bibliographically approved

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Garrido, Mario

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Citation style
  • apa
  • harvard1
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Language
  • de-DE
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Output format
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