A Pipelined FFT Architecture for Real-Valued Signals
2009 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 56, no 12, 2634-2643 p.Article in journal (Refereed) Published
This paper presents a new pipelined hardware archi-tecture for the computation of the real-valued fast Fourier trans-form (RFFT). The proposed architecture takes advantage of the re-duced number of operations of the RFFT with respect to the com-plex fast Fourier transform (CFFT), and requires less area whileachieving higher throughput and lower latency.The architecture is based on a novel algorithm for the computa-tion of the RFFT, which, contrary to previous approaches, presentsa regular geometry suitable for the implementation of hardwarestructures. Moreover, the algorithm can be used for both the deci-mation in time (DIT) and decimation in frequency (DIF) decompo-sitions of the RFFT and requires the lowest number of operationsreported for radix 2.Finally, as in previous works, when calculating the RFFT theoutput samples are obtained in a scrambled order. The problemof reordering these samples is solved in this paper and a pipelinedcircuit that performs this reordering is proposed.
Place, publisher, year, edition, pages
IEEE , 2009. Vol. 56, no 12, 2634-2643 p.
Decimation in frequency, decimation in time, fast Fourier transform (FFT), memory reduction, pipelined archi- tecture, real-valued signals, reordering circuit.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-70361DOI: 10.1109/TCSI.2009.2017125OAI: oai:DiVA.org:liu-70361DiVA: diva2:438521