A 500-MHz low-voltage programmable gain amplifier for HD video in 65-nm CMOS
2010 (English)In: Proceedings of 28th IEEE Norchip Conference., NORCHIP'10, Tampere: www.ieee.org , 2010, 1-4 p.Conference paper (Refereed)
This work describes the implementation of a 1.2-V programmable gain amplifier (PGA) for high-definition (HD) video digitizers in a 65-nm digital CMOS process. The “pseudo” switched-capacitor (SC) PGA architecture buffers the video signal, without switching, during the active video. The SC circuitry is used for setup of DC operating point during horizontal and vertical blanking periods. Additionally, it compensates for the `sync-tip' of analog video signals to an equal blanking level for increased dynamic range to the digitizer following the PGA. The operational transconductance amplifier (OTA) employed as main amplifier in the PGA is a pseudo-differential, positive-feedback input stage architecture with a common-mode feedforward (CMFF) technique. The common-mode feedback (CMFB) is provided once two OTAs are cascaded. Schematic-level simulation results show that the OTA maintains a -3-dB bandwidth of 550 MHz, while keeping the distortion HD3 at -60 dB for a 30-MHz, 850 mVpp high definition video signal. The 88 dB DC gain is distributed among four OTA stages and the overall, combined PGA achieves a signal-to-noise ratio of 63 dB. Due to only two stacked transistors, it achieves high output swing of ±0.85 V, 1240 V/μs slew rate while consuming 10.4 mW power.
Place, publisher, year, edition, pages
Tampere: www.ieee.org , 2010. 1-4 p.
CMOS analog integrated circuits, feedforward amplifiers, switched capacitor circuits, programmable gain amplifier.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-70366DOI: 10.1109/NORCHIP.2010.5669450ISBN: 978-1-4244-8971-8ISBN: 978-1-4244-8972-5OAI: oai:DiVA.org:liu-70366DiVA: diva2:438571
NORCHIP'10, 15-16 November 2010,Tampere, Finland