Low-Complexity Parallel Evaluation of Powers Exploiting Bit-Level Redundancy
2010 (English)In: Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 / [ed] Michael B. Matthews, Washington, DC, USA: IEEE Computer Society , 2010, 1168-1172 p.Conference paper (Refereed)
In this work, we investigate the problem of computing any requested set of power terms in parallel using summations trees. This problem occurs in applications like polynomial approximation, Farrow filters (polynomial evaluation part) etc. In the proposed technique, the partial product of each power term is initially computed independently. A redundancy check is then made in each and among all partial products matrices at bit level. The redundancy here relates to the fact that same three partial products may be present in more than one columns, and, hence, can be mapped to the same full adder. The proposed algorithm is tested for different sets of powers and wordlengths to exploit the sharing potential.
Place, publisher, year, edition, pages
Washington, DC, USA: IEEE Computer Society , 2010. 1168-1172 p.
, Asilomar Conference on Signals, Systems and Computers. Conference Record, ISSN 1058-6393
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-70453DOI: 10.1109/ACSSC.2010.5757714ISBN: 978-1-4244-9722-5OAI: oai:DiVA.org:liu-70453DiVA: diva2:439644
Signals, Systems and Computers (ASILOMAR), 2010, 7-10 Nov. 2010 , Pacific Grove, CA, USA