Calibration of high-resolution flash ADCS based on histogram test methods
2010 (English)In: Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on, IEEE , 2010, 114-117 p.Conference paper (Other academic)
In this paper a calibration technique for high-resolution, flash analog- to-digital converters (ADCs) based on histogram test methods is proposed. A probability density function, PDF, generator circuit is utilized to generate a triangular signal with a constant PDF, i.e., uniform distribution, as a test signal. In the proposed technique both offset estimation and trimming are performed without imposing any changes on the comparator structure in the ADC. The proposed algorithm estimates the offset values and stores them in a RAM. The trimming circuit uses the stored values and performs the trimming by adjusting the reference voltages to the comparators. An 8-bit flash ADC with a 1-V reference voltage, a comparator offset distribution with σos ≈ 30 mV, and a 10-bit test signal with about 3% nonlinearity are used in the simulations. The results show that the calibration improves the DNL and INL from about 3.6/3.9 LSB to about 0.9/0.75 LSB, respectively.
Place, publisher, year, edition, pages
IEEE , 2010. 114-117 p.
RAM;calibration technique;comparator;generator circuit;high-resolution flash analog-to-digital converter;histogram test method;offset estimation;offset trimming;probability density function;triangular signal generation;trimming circuit;uniform distribution;voltage 1 V;word length 10 bit;word length 8 bit;analogue-digital conversion;calibration;comparators (circuits);probability;random-access storage;signal generators;
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-70623DOI: 10.1109/ICECS.2010.5724467ISBN: 978-1-4244-8155-2OAI: oai:DiVA.org:liu-70623DiVA: diva2:440978
2010 IEEE International Conference on Electronics, Circuits, and Systems, 12-15 Dec. 2010, Athens, Greece