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Inter-channel offset and gain mismatch correction for time-interleaved pipelined ADCs
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2011 (English)In: Microelectronics Journal, ISSN 0959-8324, Vol. 42, no 1, 158-164 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a digital background calibration technique to compensate inter-channel gain and offset errors in parallel, pipelined analog-to-digital converters (ADCs). By using an extra analog path, calibration of each ADC channel is done without imposing any changes on the digitizing structure, i.e., keeping each channel completely intact. The extra analog path is simplified using averaging and chopping concepts, and it is realized in a standard 0.18‐μm CMOS technology. The complexity of the analog part of the proposed calibration system is same for a different number of channels.

Simulation results of a behavioral 12-bit, dual channel, pipelined ADC show that offset and gain error tones are improved from −56.5 and −58.3 dB before calibration to about −86.7 and −103 dB after calibration, respectively.

Place, publisher, year, edition, pages
Oxford, UK: Elsevier, 2011. Vol. 42, no 1, 158-164 p.
Keyword [en]
Analog–digital conversion; Calibration; Chopping; Gain error; Offset error; Parallel pipelined ADC
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:liu:diva-70616DOI: 10.1016/j.mejo.2010.08.014ISI: 000286999400019OAI: oai:DiVA.org:liu-70616DiVA: diva2:440992
Available from: 2011-09-14 Created: 2011-09-14 Last updated: 2017-12-08Bibliographically approved

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Wikner, Jacob

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