FPGA implementation of rate-compatible QC-LDPC code decoder
2011 (English)Conference paper (Other academic)
The use of rate-compatible error correcting codes offers severaladvantages as compared to the use of fixed-rate codes: a smooth adaptationto the channel conditions, the possibility of incremental Hybrid ARQschemes, as well as simplified code representations in the encoder anddecoder. In this paper, the implementation of a decoder for rate-compatiblequasi-cyclic LDPC codes is considered. The decoder uses check node mergingto increase the convergence speed of the algorithm. Check node mergingallows the decoder to achieve the same performance with a significantlylower number of iterations, thereby increasing the throughput.
The feasibility of a check node merging decoder is investigated for codesfrom IEEE 802.16e and IEEE 802.11n. The faster convergence rate of the checknode merging algorithm allows the decoder to be implemented using lowerparallelization factors, thereby reducing the logic complexity. The designshave been synthesized to an Altera Cyclone II FPGA, and results showsignificant increases in throughput at high SNR.
Place, publisher, year, edition, pages
2011. 777-780 p.
IdentifiersURN: urn:nbn:se:liu:diva-70821DOI: 10.1109/ECCTD.2011.6043844ISBN: 978-1-4577-0616-5 (online)ISBN: 978-1-4577-0617-2 (print)OAI: oai:DiVA.org:liu-70821DiVA: diva2:441906
European Conference on Circuit Theory and Design, August 29-31, Linköping, Sweden