Ultra-low power FIR filter using STSC-CVL logic
2011 (English)In: 2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011, IEEE , 2011, 1-4 p.Conference paper (Other academic)
The paper shows the implementation of digital FIR filter using ultra-low power logic components. Source coupled logic is used and operated at sub-threshold region to achieve low power consumption while keeping a satisfactory output swing. The STSCL (sub-threshold source coupled logic) circuit is added with controllable voltage-level feature to minimize overall leakage current flow, including both gate leakage and sub-threshold. Seven-stage ring oscillators are implemented in CMOS, STSCL and our proposed logic at similar supply voltage to observe the differences with power consumption for the proposed technique came at nW range. Later on the FIR was design in both CMOS and proposed with measurement results shown in the paper. All measurements for are shown using 65 nm process technology, at a supply voltage of 0.5 V.
Place, publisher, year, edition, pages
IEEE , 2011. 1-4 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-70923DOI: 10.1109/ICICDT.2011.5783230ISBN: 978-1-4244-9019-6OAI: oai:DiVA.org:liu-70923DiVA: diva2:442314
2011 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT 2011, 2-4 May, Kaohsiung, Taiwan