On the efficient computation of single-bit input word length pipelined FFTs
2011 (English)In: IEICE ELECTRONICS EXPRESS, ISSN 1349-2543, Vol. 8, no 17, 1437-1443 p.Article in journal (Refereed) Published
This letter describes an efficient architecture for the computation of fast Fourier transform (FFT) algorithms with single-bit input. The proposed architecture is aimed for the first stages of pipelined FFT architectures, processing one sample per clock cycle, hence making it suiable for real-time FFT computation. Since natural input order pipeline FFTs use large memories in the early stages, it is important to keep the word length shorter in the beginning of the pipeline. By replacing the initial butterflies and rotators of an architecture with that of the proposed block, the memory requirements can be significantly reduced. Comparisons with the commonly used single delay feedback (SDF) architecture show that more than 50% of the required memory can be saved in some cases.
Place, publisher, year, edition, pages
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG MINATO-KU SHIBAKOEN 3 CHOME, TOKYO, 105, JAPAN , 2011. Vol. 8, no 17, 1437-1443 p.
FFT algorithm, complexity, single-bit, word length
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-71646DOI: 10.1587/elex.8.1437ISI: 000295835400011OAI: oai:DiVA.org:liu-71646DiVA: diva2:451816
Funding Agencies|NED University, Pakistan||Higher Education Commission, Pakistan||CENIIT at Linkoping University, Sweden||Innovative Navigation using new GNSS Signals with Hybridised Technologies (INSIGHT)||UK Engineering and Physical Sciences Research Council (EPSRC)||2011-10-272011-10-272015-03-11