Optimum Circuits for Bit Reversal
2011 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, Vol. 58, no 10, 657-661 p.Article in journal (Refereed) Published
This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2011. Vol. 58, no 10, 657-661 p.
Bit reversal, fast Fourier transform (FFT), pipelined architecture
National CategoryEngineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-71782DOI: 10.1109/TCSII.2011.2164141ISI: 000296009700009OAI: oai:DiVA.org:liu-71782DiVA: diva2:453943
Funding Agencies|Spanish Ministry of Education|AP2005-0544|Spanish National Research and Development Program|TEC2008-02148|Swedish ELLIIT Program||2011-11-042011-11-042015-03-11