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Optimum Circuits for Bit Reversal
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
University of Politecn Madrid.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.ORCID iD: 0000-0003-3470-3911
2011 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, 657-661 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents novel circuits for calculating bit reversal on a series of data. The circuits are simple and consist of buffers and multiplexers connected in series. The circuits are optimum in two senses: they use the minimum number of registers that are necessary for calculating the bit reversal and have minimum latency. This makes them very suitable for calculating the bit reversal of the output frequencies in hardware fast Fourier transform (FFT) architectures. This brief also proposes optimum solutions for reordering the output frequencies of the FFT when different common radices are used, including radix-2, radix-2(k), radix-4, and radix-8.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2011. Vol. 58, no 10, 657-661 p.
Keyword [en]
Bit reversal, fast Fourier transform (FFT), pipelined architecture
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-71782DOI: 10.1109/TCSII.2011.2164141ISI: 000296009700009OAI: oai:DiVA.org:liu-71782DiVA: diva2:453943
Note

Funding Agencies|Spanish Ministry of Education|AP2005-0544|Spanish National Research and Development Program|TEC2008-02148|Swedish ELLIIT Program||

Available from: 2011-11-04 Created: 2011-11-04 Last updated: 2017-12-08

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Garrido Gálvez, MarioGustafsson, Oscar

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  • apa
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