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CMOS RF Power Amplifiers for Wireless Communications
Linköping University, Department of Electrical Engineering, Electronic Devices. Linköping University, The Institute of Technology.
2011 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The wireless market has experienced a remarkable development and growth since the introduction of the first modern mobile phone systems, with a steady increase in the number of subscribers, new application areas, and higher data rates. As mobile phones and wireless connectivity have become consumer mass markets, the prime goal of the IC manufacturers is to provide low-cost solutions.

The power amplifier (PA) is a key building block in all RF transmitters. To lower the costs and allow full integration of a complete radio System-on-Chip (SoC), it is desirable to integrate the entire transceiver and the PA in a single CMOS chip. While digital circuits benefit from the technology scaling, it is becoming harder to meet the stringent requirements on linearity, output power, bandwidth, and efficiency at lower supply voltages in traditional PA architectures. This has recently triggered extensive studies to investigate the impact of different efficiency enhancement and linearization techniques, like polar modulation and outphasing, in nanometer CMOS technologies.

This thesis addresses the potential of integrating linear and power-efficient PAs in nanometer CMOS technologies at GHz frequencies. In total eight amplifiers have been designed - two linear Class-A PAs, two switched Class-E PAs, and four Class-D PAs linearized in outphasing configurations. Based on the outphasing PAs, amplifier models and predistorters have been developed and evaluated for uplink (terminal) and downlink (base station) signals.

The two linear Class-A PAs with LC-based and transformer-based input and interstage matching networks were designed in a 65nm CMOS technology for 2.4GHz 802.11n WLAN. For a 72.2Mbit/s 64-QAM 802.11n OFDM signal with PAPR of 9.1dB, both PAs fulfilled the toughest EVM requirement in the standard at average output power levels of +9.4dBm and +11.6dBm, respectively. The two PAs were among the first PAs implemented in a 65nm CMOS technology.

The two Class-E PAs, intended for DECT and Bluetooth, were designed in 130nm CMOS and operated at low ‘digital’ supply voltages. The PAs delivered +26.4 and +22.7dBm at 1.5V and 1.0V supply voltages with PAE of 30% and 36%, respectively. The Bluetooth PA was based on thin oxide devices and the performance degradation over time for a high level of oxide stress was evaluated.

The four Class-D outphasing PAs were designed in 65nm, 90nm, and 130nm CMOS technologies. The first outphasing design was based on a Class-D stage utilizing a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5V supply voltage in a 65nm CMOS technology without excessive device voltage stress. Two on-chip transformers combined the outputs of four Class-D stages. At 1.95GHz the PA delivered +29.7dBm with a PAE of 26.6%. The 3dB bandwidth was  1.6GHz, representing state-of-the-art bandwidth for CMOS Class-D RF PAs. After one week of continuous operation, no performance degradation was noticed. The second design was based on the same Class-D stage, but combined eight amplifier stages by four on-chip transformers in 130nm CMOS to achieve a state-of-the-art output power of +32dBm for CMOS Class-D RF PAs. Both designs met the ACLR and modulation requirements without predistortion when amplifying uplink WCDMA and 20MHz LTE signals.

The third outphasing design was based on two low-power Class-D stages in 90nm CMOS featuring a harmonic suppression technique, cancelling the third harmonic in the output spectrum which also improves drain efficiency. The proposed Class-D stage creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. A single Class-D stage delivered +5.1dBm at 1.2V supply voltage with a drain efficiency and PAE of 73% and 59%, respectively. Two Class-D stages were connected to a PCB transformer to create an outphasing amplifier, which was linear enough to amplify EDGE and WCDMA signals without the need for predistortion.

The fourth outphasing design was based on two Class-D stages  connected to an on-chip transformer with peak power of +10dBm. It was used in the development of a behavioral model structure and model-based phase-only predistortion method suitable for outphasing amplifiers to compensate for both amplitude and phase mismatches. In measurements for EDGE and WCDMA signals, the predistorter improved the margin to the limits of the spectral mask and the ACLR by more than 12dB. Based on a similar approach, an amplifier model and predistortion method were developed and evaluated for the +32dBm Class-D PA design using a downlink WCDMA signal, where the ACLR was improved by 13.5dB. A least-squares phase predistortion method was developed and evaluated for the +30dBm Class-D PA design using WCDMA and LTE uplink signals, where the ACLR was improved by approximately 10dB.

Place, publisher, year, edition, pages
Linköping: Linköping University Electronic Press , 2011. , 94 p.
Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1399
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:liu:diva-71852ISBN: 978-91-7393-059-8 (print)OAI: oai:DiVA.org:liu-71852DiVA: diva2:454627
Public defence
2011-11-25, KEY1, Key-huset, Campus Valla, Linköpings universitet, Linköping, 10:15 (Swedish)
Opponent
Supervisors
Available from: 2011-11-08 Created: 2011-11-07 Last updated: 2011-11-16Bibliographically approved
List of papers
1. A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
Open this publication in new window or tab >>A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS
2010 (English)In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 64, no 3, 241-247 p.Article in journal (Refereed) Published
Abstract [en]

This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

Place, publisher, year, edition, pages
Springer Science Business Media, 2010
Keyword
CMOS, Power amplifier, Transformers, Wireless LAN
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58661 (URN)10.1007/s10470-009-9427-2 (DOI)000280593900005 ()
Note
The original publication is available at www.springerlink.com: Jonas Fritzin and Atila Alvandpour, A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS, 2010, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (64), 3, 241-247. http://dx.doi.org/10.1007/s10470-009-9427-2 Copyright: Springer Science Business Media http://www.springerlink.com/ Available from: 2010-08-22 Created: 2010-08-20 Last updated: 2017-12-12Bibliographically approved
2. Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
Open this publication in new window or tab >>Impedance Matching Techniques in 65nm CMOS Power Amplifiers for 2.4GHz 802.11n WLAN
2008 (English)In: European Microwave Week 2008, Conference Proceedings, 27-31 October 2008, Amsterdam, The Netherlands, IEEE , 2008, 1207-1210 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper describes the design of two power amplifiers (PA) for WLAN 802.11n fabricated in 65 nm CMOS technology. Both PAs utilize 3.3V thick-gate oxide (5.2 nm) transistors and employ a two-stage differential structure, but the input and interstage matching networks are realized differently. The first PA uses LC matching networks for matching, while the second PA uses on-chip transformers. The impedance matching techniques applied for the matching networks will be described. EVM, output power levels, and spectral masks are obtained for a 72.2 Mbit/s, 64-QAM, 802.11n, OFDM signal.

Place, publisher, year, edition, pages
IEEE, 2008
Keyword
CMOS integrated circuits, impedance matching, power amplifiers, transformers, transistors, wireless LAN
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-21009 (URN)10.1109/EUMC.2008.4751677 (DOI)978-2-87487-006-4 (ISBN)
Conference
The 38th IEEE European Microwave Conference (EuMC), October 28-30, Amsterdam, The Netherlands
Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2011-11-08Bibliographically approved
3. Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
Open this publication in new window or tab >>Low Voltage Class-E Power Amplifiers for DECT and Bluetooth in 130nm CMOS
2009 (English)In: Proceedings of 9th IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), San Diego, CA, USA, January 19–21, IEEE , 2009, 1-4 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents the design of two low- voltage differential class-E power amplifiers (PA) for DECT and Bluetooth fabricated in 130 nm CMOS. In order to minimize the on-chip losses and to achieve a high efficiency at low supply voltages, the PAs do not use on-chip output matching networks. At 1.5V supply voltage, the DECT PA delivers +26.4 dBm of output power with a drain efficiency (DE) and power-added efficiency (PAE) of 41% and 30%, respectively. The Bluetooth PA delivers +22.7 dBm at IV with a DE and PAE of 48% and 36%, respectively. A continuous long-term test of 100 hours proves the reliability of the design.

Place, publisher, year, edition, pages
IEEE, 2009
Keyword
Bluetooth, CMOS integrated circuits, cordless telephone systems, differential amplifiers, power amplifiers, reliability
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-21022 (URN)10.1109/SMIC.2009.4770499 (DOI)978-1-4244-3940-9 (ISBN)
Conference
IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 2009. SiRF '09, 19-21 January, San Diego, CA, USA
Available from: 2009-09-28 Created: 2009-09-28 Last updated: 2011-11-08Bibliographically approved
4. Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
Open this publication in new window or tab >>Reliability study of a low-voltage Class-E power amplifier in 130nm CMOS
2010 (English)In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, IEEE , 2010, 1907-1910 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents reliability measurements of a differential Class-E power amplifier (PA) operating at 850MHz in 130nm CMOS. The RF performance of five samples was tested. At 1.1V, the PAs deliver +20.4–21.5dBm of output power with drain efficiencies and power-added efficiencies of 56–64% and 46–51%, respectively. After a continuous long-term test of 240 hours at elevated supply voltage of 1.4V, the output power dropped about 0.7dB.

Place, publisher, year, edition, pages
IEEE, 2010
Keyword
CMOS, efficiency, power amplifier, reliability testing
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-58725 (URN)10.1109/ISCAS.2010.5537959 (DOI)978-1-4244-5308-5 (ISBN)
Conference
IEEE International Symposium on Circuits and Systems (ISCAS), May 30th - June 2nd, Paris, France
Available from: 2010-08-24 Created: 2010-08-24 Last updated: 2011-11-08Bibliographically approved
5. Wideband Fully Integrated +30dBm Class-D Outphasing RF PA in 65nm CMOS
Open this publication in new window or tab >>Wideband Fully Integrated +30dBm Class-D Outphasing RF PA in 65nm CMOS
2011 (English)Conference paper, Published paper (Other academic)
Abstract [en]

This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +29.7dBm with 26.6% PAE at 1.95 GHz in a standard 65nm CMOS technology. The PA utilizes two on-chip transformers to combine the outputs of four Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled lowvoltage driver, to allow a 5.5V supply without excessive device voltage stress. The measured 3 dB bandwidth was 1.6 GHz (1.2-2.8 GHz). The PA was continuously operated for 168 hours (1 week) without any performance degradation. To evaluate the linearity of the outphasing PA, a WCDMA and an LTE signal (20 MHz, 16-QAM) were used. At +26.0dBm channel power for the WCDMA signal, the measured ACLR at 5MHz and 10MHz offset were -35.6 dBc and -48.4 dBc, respectively. At +22.9dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was -35.9 dBc.

Keyword
Outphasing, CMOS, power amplifier
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71857 (URN)10.1109/ISICir.2011.6131871 (DOI)978-1-61284-863-1 (ISBN)
Conference
IEEE International Symposium on Integrated Circuits (ISIC), Singapore, December 12-14
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2014-10-09Bibliographically approved
6. A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
Open this publication in new window or tab >>A +32dBm 1.85GHz Class-D Outphasing RF PA in 130nm CMOS for WCDMA/LTE
2011 (English)In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), IEEE , 2011, 127-130 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a Class-D outphasing RF Power Amplifier (PA) which can operate at a 5.5V supply and deliver +32dBm at 1.85 GHz in a standard 130nm CMOS technology. The PA utilizes four on-chip transformers to combine the outputs of eight Class-D stages. The Class-D stages utilize a cascode configuration, driven by an AC-coupled low-voltage driver, to allow a 5.5 V supply in the 1.2/2.5 V 130nm process without excessive device voltage stress. Spectral and modulation requirements were met when a WCDMA and an LTE signal (20 MHz, 16-QAM) were applied to the outphasing PA. At +28.0 dBm channel power for the WCDMA signal, the measured ACLR at 5 MHz and 10 MHz offset were −38.7 dBc and −47.0 dBc, respectively. At +24.9 dBm channel power for the LTE signal, the measured ACLR at 20MHz offset was −34.9 dBc. To the authors' best knowledge, the PA presented in this work has a 3.9 dB higher output power compared to published CMOS Class-D RF PAs.

Place, publisher, year, edition, pages
IEEE, 2011
Series
European Solid-State Circuits Conference, ISSN 1930-8833 ; 2011
Keyword
Outphasing, CMOS, power amplifier
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:liu:diva-71858 (URN)10.1109/ESSCIRC.2011.6044881 (DOI)978-1-4577-0702-5 (ISBN)978-1-4577-0703-2 (ISBN)
Conference
ESSCIRC
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2011-12-15Bibliographically approved
7. A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
Open this publication in new window or tab >>A Class-D outphasing RF amplifier with harmonic suppression in 90nm CMOS
2010 (English)In: Proceedings of the ESSCIRC, 2010, Seville: IEEE , 2010, 310-313 p.Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a low-power Class-D stage featuring a new harmonic reduction technique, which cancels the 3rd harmonic and reduces the 5th harmonic. The technique creates a voltage level of VDD/2 from a single supply voltage to shape the drain voltage, uses only digital circuits and eliminates the short-circuit current present in inverter-based Class-D stages. From a single Class-D stage operating at 900MHz, the measured output power is +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% for a 1.2V supply, while 2nd to 4th harmonics are measured to be -37dBc without any filtering. Connecting two Class-D stages to a PCB-mounted transformer in an outphasing configuration, the overall amplifier is linear enough to amplify EDGE 8-PSK and WCDMA modulated signals at 900MHz without pre-distortion of the input signals or any other linearization technique.

Place, publisher, year, edition, pages
Seville: IEEE, 2010
Series
ESSCIRC, ISSN 1930-8833 ; 2010
Keyword
CMOS integrated circuits, code division multiple access, harmonic distortion, invertors, linearisation techniques, phase shift keying, power amplifiers, radiofrequency amplifiers, short-circuit currents
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-65459 (URN)10.1109/ESSCIRC.2010.5619706 (DOI)978-1-4244-6662-7 (ISBN)
Conference
36th European Solid State Circuits Conference (ESSCIRC), 14-16 September, Seville, Spain
Available from: 2011-02-08 Created: 2011-02-08 Last updated: 2011-11-08Bibliographically approved
8. Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
Open this publication in new window or tab >>Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS
Show others...
2011 (English)In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 58, no 10, 642-646 p.Article in journal (Refereed) Published
Abstract [en]

This brief presents a behavioral model structure and a model-based phase-only predistortion method that are suitable for outphasing RF amplifiers. The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. The method has been used for enhanced data rates for GSM evolution (EDGE) and wideband code-division multiple-access (WCDMA) signals applied to a Class-D outphasing RF amplifier with an on-chip transformer used for power combining in 90-nm CMOS. The measured peak power at 2 GHz was +10.3 dBm with a drain efficiency and power-added efficiency of 39% and 33%, respectively. For an EDGE 8 phase-shift-keying (8-PSK) signal with a phase error of 3 degrees between the two input outphasing signals, the measured power at 400 kHz offset was -65.9 dB with predistortion, compared with -53.5 dB without predistortion. For a WCDMA signal with the same phase error between the input signals, the measured adjacent channel leakage ratio at 5-MHz offset was -50.2 dBc with predistortion, compared with -38.0 dBc without predistortion.

Keyword
Amplifier, Complementary metal-oxide-semiconductor (CMOS), Linearization, Outphasing
National Category
Control Engineering
Identifiers
urn:nbn:se:liu:diva-71781 (URN)10.1109/TCSII.2011.2164149 (DOI)000296009700006 ()
Funder
Swedish Foundation for Strategic Research Swedish Research CouncileLLIIT - The Linköping‐Lund Initiative on IT and Mobile Communications
Available from: 2011-11-04 Created: 2011-11-04 Last updated: 2017-12-08Bibliographically approved
9. Design and Analysis of a Class-D Stage with Harmonic Suppression
Open this publication in new window or tab >>Design and Analysis of a Class-D Stage with Harmonic Suppression
2012 (English)In: Transactions on Circuits and Systems–I: Regular Papers, ISSN 1549-8328, Vol. 59, no 6, 1178-1186 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents the design and analysis of a low-power Class-D stage in 90nm CMOS featuring a harmonic suppression technique, which cancels the 3rd harmonic by shaping the output voltage waveform. Only digital circuits are used and the short-circuit current present in Class-D inverterbased output stages is eliminated, relaxing the buffer requirements. Using buffers with reduced drive strength for the output stage reduces the 5th harmonic at the output, as the rise and fall time of the output voltage increase. Operating at 900MHz, the measured output power was +5.1dBm with Drain Efficiency (DE) and Power-Added Efficiency (PAE) of 73% and 59% at 1.2V. The 3rd and 5th harmonics were suppressed by 34dB and 4dB, respectively, compared to an inverter-based Class-D stage.1

Place, publisher, year, edition, pages
IEEE, 2012
Keyword
Radio transmitter, CMOS, harmonic rejection
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71859 (URN)10.1109/TCSI.2011.2173389 (DOI)000304825700004 ()
Conference
EEE Transactions on Circuits and Systems–I: Regular Papers
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2012-06-29Bibliographically approved
10. Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers
Open this publication in new window or tab >>Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers
2011 (English)Manuscript (preprint) (Other academic)
Abstract [en]

This paper presents a direct model structure for describing class-D outphasing amplifiers and a method for digitally predistorting these amplifiers. The direct model structure is based on modeling differences in gain and delay, nonlinear interactions between the two paths and differences in the amplifier behavior. The digital predistortion method is designed to operate only on the input signals’ phases, to correct for both amplitude and phase mismatches. This eliminates the need for additional voltage supplies to compensate for gain mismatch.

Model and predistortion performance are evaluated on a 32 dBm peak output power, class-D outphasing amplifier in CMOS with on-chip transformers. The excitation signal is a 5 MHz wide downlinkWCDMA signal with peak-to-average power ratio (PAPR) of 9.5 dB. Using the proposed digital predistorter the 5 MHz adjacent channel leakage power ratio (ACLR) was improved by 13.5 dB, from -32.1 dBc to -45.6 dBc. The 10 MHz ACLR was improved by 6.4 dB, from -44.3 dBc to -50.7 dBc, making the amplifier pass the ACLR requirements.

Keyword
Power amplifiers, behavioral modeling, digital predistortion, outphasing amplifier, LINC
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71860 (URN)
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2011-11-08Bibliographically approved
11. Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
Open this publication in new window or tab >>Least-Squares Phase Predistortion of a +30dBm Class-D Outphasing RF PA in 65nm CMOS
2013 (English)In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 60, no 7, 1915-1928 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents a model-based phase-only predistortion method suitable for outphasing radio frequency (RF) power amplifiers (PA). The predistortion method is based on a model of the amplifier with a constant gain factor and phase rotation for each outphasing signal, and a predistorter with phase rotation only. Exploring the structure of the outphasing PA, the problem can be reformulated from a nonconvex problem into a convex least-squares problem, and the predistorter can be calculated analytically. The method has been evaluted for 5MHz Wideband Code-Division Multiple Access (WCDMA) and Long Term Evolution (LTE) uplink signals with Peak-to-Average Power Ratio (PAPR) of 3.5 dB and 6.2 dB, respectively, applied to a fully integrated Class-D outphasing RF PA in 65nm CMOS. At 1.95 GHz for a 5.5V supply voltage, the measured output power of the PA was +29.7dBm with a power-added efficiency (PAE) of 26.6 %. For the WCDMA signal with +26.0dBm of channel power, the measured Adjacent Channel Leakage Ratio (ACLR) at 5MHz and 10MHz offsets were -46.3 dBc and -55.6 dBc with predistortion, compared to -35.5 dBc and -48.1 dBc without predistortion. For the LTE signal with +23.3dBm of channel power, the measured ACLR at 5MHz offset was -43.5 dBc with predistortion, compared to -34.1 dBc without predistortion.

Keyword
Outphasing, amplifier, linearization, predistortion, complementary metal-oxide-semiconductor (CMOS)
National Category
Engineering and Technology
Identifiers
urn:nbn:se:liu:diva-71862 (URN)10.1109/TCSI.2012.2230507 (DOI)000322331200020 ()
Available from: 2011-11-08 Created: 2011-11-08 Last updated: 2017-12-08Bibliographically approved

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