Using Partial Reconfigurability to aid Debugging of FPGA Designs
2011 (English)Conference paper (Refereed)
This paper discusses the use of partial reconfigurability in Xilinx FPGA designs in order to aid debugging. A debugging framework is proposed where the use of partial reconfigurability can allow for added flexibility by allowing a debugger to decide at run time what debugging module to use. This paper also presents an open source debugging tool which allows a user to read-out the contents of memory blocks in Xilinx designs without needing to use any JTAG adapter. This allows a user to debug an FPGA in situations which would otherwise be difficult, i.e. in the field.
Place, publisher, year, edition, pages
2011. 215-220 p.
IdentifiersURN: urn:nbn:se:liu:diva-72273DOI: 10.1109/SPL.2011.5782651OAI: oai:DiVA.org:liu-72273DiVA: diva2:458860
VII Southern Conference on Programmable Logic (SPL)