A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-um CMOS for medical implant devices
2011 (English)In: Proceedings of the IEEE European Solid-State Circuits Conference (ESSCIRC), Helsinki, Finland: IEEE Solid-State Circuits Society, 2011, 467-470 p.Conference paper (Refereed)
This paper describes an ultra-low-power SAR ADC in 0.13-um CMOS technology for medical implant devices. It utilizes an ultra-low-power design strategy, imposing maximum simplicity in ADC architecture, low transistor count, low-voltage low-leakage circuit techniques, and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. Furthermore, a dual-supply scheme allows the SAR logic to operate at 400mV. The ADC has been fabricated in 0.13-um CMOS. In 1.0-V single-supply mode, the ADC consumes 65nW at a sampling rate of 1kS/s, while in dual-supply mode (1.0V for analog and 0.4V for digital) it consumes 53nW (18% reduction) and achieves the same ENOB of 9.12. 24% of the 53-nW total power is due to leakage. To the authors' best knowledge, this is the lowest reported power consumption of a 10-bit ADC for such sampling rates.
Place, publisher, year, edition, pages
Helsinki, Finland: IEEE Solid-State Circuits Society, 2011. 467-470 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-73016DOI: 10.1109/ESSCIRC.2011.6045008OAI: oai:DiVA.org:liu-73016DiVA: diva2:464885