Power Consumption Bounds for SAR ADCs
2011 (English)In: European Conference on Circuit Theory and Design (ECCTD), Linköping, Sweden: IEEE conference proceedings, 2011, 556-559 p.Conference paper (Refereed)
Power consumption is an important limitation to analog-to-digital converters. The objective of this paper is to estimate a lower bound to the power consumption of successive approximation analog-to-digital converters. This is an extension of our previous work which was limited to pipelined and flash architectures. We find that the power consumption in our case is bounded by capacitor mismatch or thermal noise at high resolution and by digital switching power at low resolution. We also evaluate our methods and the estimated lower bound is compatible with experimental data.
Place, publisher, year, edition, pages
Linköping, Sweden: IEEE conference proceedings, 2011. 556-559 p.
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-73030DOI: 10.1109/ECCTD.2011.6043594ISBN: 978-1-4577-0617-2 (Print)ISBN: 978-1-4577-0616-5 (online)OAI: oai:DiVA.org:liu-73030DiVA: diva2:464991
20th European Conference on Circuit Theory and Design, Linköping, 29-31 Aug. 2011