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Assertion Based Verification on Senior DSP
Linköping University, Department of Electrical Engineering, Computer Engineering. Linköping University, The Institute of Technology.
2011 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Digital designs are often very large and complex, this makes locating and fixing a bug very hard and time consuming. Often more than half of the development time is spent on verification. Assertion based verification is a method that uses assertions that can help to improve the verification time. Simulating with assertions provides more information that can be used to locate and correct a bug. In this master thesis assertions are discussed and implemented in Senior DSP processor.

Place, publisher, year, edition, pages
2011. , 45 p.
Keyword [en]
SystemVerilog, Verification, Assertion, DSP
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
URN: urn:nbn:se:liu:diva-74392ISRN: LiTH-ISY-EX--11/4538--SEOAI: diva2:483658
Subject / course
Computer Engineering
Available from: 2012-02-14 Created: 2012-01-25 Last updated: 2012-02-14Bibliographically approved

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Computer EngineeringThe Institute of Technology
Electrical Engineering, Electronic Engineering, Information Engineering

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ReferencesLink to record
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