Assertion Based Verification on Senior DSP
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Digital designs are often very large and complex, this makes locating and fixing a bug very hard and time consuming. Often more than half of the development time is spent on verification. Assertion based verification is a method that uses assertions that can help to improve the verification time. Simulating with assertions provides more information that can be used to locate and correct a bug. In this master thesis assertions are discussed and implemented in Senior DSP processor.
Place, publisher, year, edition, pages
2011. , 45 p.
SystemVerilog, Verification, Assertion, DSP
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-74392ISRN: LiTH-ISY-EX--11/4538--SEOAI: oai:DiVA.org:liu-74392DiVA: diva2:483658
Subject / course