Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support
2012 (English)In: Journal of Signal Processing Systems, ISSN 1939-8018, Vol. 66, no 1, 25-41 p.Article in journal (Refereed) Published
This paper presents a unified, radix-4 implementation of turbo decoder, covering multiple standards such as DVB, WiMAX, 3GPP-LTE and HSPA Evolution. The radix-4, parallel interleaver is the bottleneck while using the same turbo-decoding architecture for multiple standards. This paper covers the issues associated with design of radix-4 parallel interleaver to reach to flexible turbo-decoder architecture. Radix-4, parallel interleaver algorithms and their mapping on to hardware architecture is presented for multi-mode operations. The overheads associated with hardware multiplexing are found to be least significant. Other than flexibility for the turbo decoder implementation, the low silicon cost and low power aspects are also addressed by optimizing the storage scheme for branch metrics and extrinsic information. The proposed unified architecture for radix-4 turbo decoding consumes 0.65 mm(2) area in total in 65 nm CMOS process. With 4 SISO blocks used in parallel and 6 iterations, it can achieve a throughput up to 173.3 Mbps while consuming 570 mW power in total. It provides a good trade-off between silicon cost, power consumption and throughput with silicon efficiency of 0.005 mm(2)/Mbps and energy efficiency of 0.55 nJ/b/iter.
Place, publisher, year, edition, pages
Springer Verlag (Germany) , 2012. Vol. 66, no 1, 25-41 p.
Turbo codes, VLSI implementation, Radix-4, Parallel interleaver, Multimode
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-75110DOI: 10.1007/s11265-010-0521-6ISI: 000299530700004OAI: oai:DiVA.org:liu-75110DiVA: diva2:504548
Funding Agencies|European Commission||Ericson AB||Infineon Austria AG||IMEC||Lund University||KU-Leuven||2012-02-212012-02-172012-02-21