Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011 (English)In: 3D-TEST, 2011Conference paper (Refereed)
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs and 3D TSV-SICs with two chips in the stack. We have implemented our techniques and experiments show significant reduction of test cost.
Place, publisher, year, edition, pages
National CategoryComputer and Information Science
IdentifiersURN: urn:nbn:se:liu:diva-77287OAI: oai:DiVA.org:liu-77287DiVA: diva2:526213
2nd IEEE Intl. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Anaheim, CA, USA, September 22-23, 2011