Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
2012 (English)In: VLSI 2012, IEEE , 2012Conference paper, Presentation (Refereed)
Test planning for core-based 3D stacked ICs with trough-silicon vias (3D TSV-SIC) is different from test planning for non-stacked ICs as the same test schedule cannot be applied both at wafer sort and package test. In this paper, we assume a test flow where each chip is tested individually at wafer sort and jointly at package test. We define cost functions and test planning optimization algorithms for non-stacked ICs, 3D TSVSICs with two chips and 3D TSV-SICs with an arbitrary number of chips. We have implemented our techniques and experiments show significant reduction of test cost.
Place, publisher, year, edition, pages
IEEE , 2012.
, VLSI Design, ISSN 1063-9667
Computer and Information Science
IdentifiersURN: urn:nbn:se:liu:diva-77289DOI: 10.1109/VLSID.2012.111ISBN: 978-076954638-4OAI: oai:DiVA.org:liu-77289DiVA: diva2:526217
25th International Conference on VLSI Design (VLSI 2012), Hyderabad, India, January 7-11, 2012