liu.seSearch for publications in DiVA
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Reliability-Aware Instruction Set Customization for ASIPs with Hardened Logic
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
Institute of Computer Science & Engineering (ITEC), Karlsruhe Institute of Technology (KIT), Germany.
Linköping University, Department of Computer and Information Science, Software and Systems. Linköping University, The Institute of Technology.
Show others and affiliations
2012 (English)In: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2012), Seoul, Korea, August 19-22, 2012., 2012Conference paper, Published paper (Refereed)
Abstract [en]

Application-specific instruction-set processors (ASIPs) allow the designer to extend the instruction set of the base processor with selected custom instructions to tailor-fit the application.In this paper, with the help of a motivational example, we first demonstrate that different custom instructions are vulnerable to faults with varying probabilities. This shows that by ignoring the vulnerability to faults, traditional methods of instruction set customization can provide no guarantees on the reliability of the system. Apart from such inherent disparity in error vulnerability across custom instructions, each custom instruction can have multiple implementation choices corresponding to varying hardened levels. Hardening reduces the vulnerability to errors but this comes at the overhead of area costs and reduced performance gain. In this paper, we propose a framework to select custom instructions and their respective hardening levels such that reliability is optimized while the performance gain is satisfied and area costs are met as well. Our framework is based on a novel analytical method to compute the overall system reliability based on the probability of failure of individual instructions. Wide range of experiments that were conducted illustrate how our tool navigates the design space to reveal interesting tradeoffs.

Place, publisher, year, edition, pages
2012.
National Category
Computer and Information Science
Identifiers
URN: urn:nbn:se:liu:diva-78639DOI: 10.1109/RTCSA.2012.28ISBN: 978-1-4673-3017-6 (print)ISBN: 978-0-7695-4824-1 (print)OAI: oai:DiVA.org:liu-78639DiVA: diva2:534204
Conference
RTCSA12
Available from: 2012-06-15 Created: 2012-06-15 Last updated: 2017-02-14

Open Access in DiVA

No full text

Other links

Publisher's full text

Authority records BETA

Bordoloi, Unmesh D.Tanasa, BogdanEles, PetruPeng, Zebo

Search in DiVA

By author/editor
Bordoloi, Unmesh D.Tanasa, BogdanEles, PetruPeng, Zebo
By organisation
Software and SystemsThe Institute of Technology
Computer and Information Science

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 193 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • oxford
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf