Live Demonstration of Mismatch Compensation for Time-Interleaved ADCs
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
The purpose of this thesis is to demonstrate the effects of mismatch errors that occur in time-interleaved analog-to-digital converters (TI-ADC) and how these are compensated for by proprietary methods from Signal Processing Devices Sweden AB. This will be demonstrated by two different implementations, both based on the combined digitizer/generator SDR14. These demonstrations shall be done in a way that is easy to grasp for people with limited knowledge in signal processing.
The first implementation is an analog video demo where an analog video signal is sampled by such an TI-ADC in the SDR14, and then converted back to analog and displayed with the help of a TV tuner. The mismatch compensation can be turned on and off and the difference on the resulting video image is clearly visible.
The second implementation is a digital communication demo based on W-CDMA, implemented on the FPGA of the SDR14. Four parallel W-CDMA signals of 5 MHz are sent and received by the SDR14. QPSK, 16-QAM, and 64-QAM modulated signals were successfully sent and the mismatch effects were clearly visible in the constellation diagrams. Techniques used are, for example: root-raised cosine pulse shaping, RF modulation, carrier recovery, and timing recovery.
Place, publisher, year, edition, pages
2012. , 72 p.
interleaving, analog-to-digital converter, digital communication, FPGA, analog video, carrier recovery, synchronization, RF modulation, SDR14
Signal Processing Communication Systems
IdentifiersURN: urn:nbn:se:liu:diva-78709ISRN: LiTH-ISY-EX--12/4570--SEOAI: oai:DiVA.org:liu-78709DiVA: diva2:535413
Signal Processing Devices Sweden AB
Subject / course
2012-06-07, Signalen, Linköpings Universitet, Linköping, 10:15 (Swedish)