Automatic Test Program Generation Using Executing Trace Based Constraint Extraction for Embedded Processors
2013 (English)In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, Vol. 21, no 7, 1220-1233 p.Article in journal (Refereed) Published
Software-based self-testing (SBST) has been a promising method for processor testing, but the complexity of the state-of-art processors still poses great challenges for SBST. This paper utilizes the executing trace collected during executing training programs on the processor under test to simplify mappings and functional constraint extraction for ports of inner components, which facilitate structural test generation with constraints at gate level, and automatic test instruction generation (ATIG) even for hidden control logic (HCL). In addition, for sequential HCL, we present a test routine generation technique on the basis of an extended finite state machine, so that structural patterns for combinational subcircuits in the sequential HCL can be mapped into the test routines to form a test program. Experimental results demonstrate that the proposed ATIG method can achieve good structural fault coverage with compact test programs on modern processors.
Place, publisher, year, edition, pages
IEEE Press, 2013. Vol. 21, no 7, 1220-1233 p.
Constraint extraction, instruction testing, processor self-testing, software-based self-testing (SBST), test program generation.
Computer and Information Science
IdentifiersURN: urn:nbn:se:liu:diva-79882DOI: 10.1109/TVLSI.2012.2208130ISI: 000320946200005OAI: oai:DiVA.org:liu-79882DiVA: diva2:544448