A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for Medical Implant Devices
2012 (English)In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, Vol. 47, no 7, 1585-1593 p.Article in journal (Refereed) Published
This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch boot-strapping and extra reset voltage. Furthermore, a dual-supply voltage scheme allows the SAR logic to operate at 0.4 V, reducing the overall power consumption of the ADC by 15% without any loss in performance. The ADC was fabricated in 0.13-mu m CMOS. In dual-supply mode (1.0 V for analog and 0.4 V for digital), the ADC consumes 53 nW at a sampling rate of 1 kS/s and achieves the ENOB of 9.1 bits. The leakage power constitutes 25% of the 53-nW total power.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2012. Vol. 47, no 7, 1585-1593 p.
ADC, analog-to-digital conversion, leakage power consumption, low-power electronics, medical implant devices, successive approximation
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-80792DOI: 10.1109/JSSC.2012.2191209ISI: 000306913500008OAI: oai:DiVA.org:liu-80792DiVA: diva2:548254