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An Analog Receiver Front-End for Capacitive Body-Coupled Communication
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
Linköping University, Department of Electrical Engineering, Electronics System. Linköping University, The Institute of Technology.
2012 (English)In: NORCHIP, 2012, IEEE , 2012, p. 1-4Conference paper, Poster (with or without abstract) (Other academic)
##### Abstract [en]

This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/√Hz at 6.8 mW.

##### Place, publisher, year, edition, pages
IEEE , 2012. p. 1-4
##### National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
##### Identifiers
ISBN: 978-1-4673-2222-5 (print)ISBN: 978-1-4673-2221-8 (print)OAI: oai:DiVA.org:liu-84302DiVA, id: diva2:558641
##### Conference
30th Norchip Conference 2012, The Nordic Microelectronics event, 12-13 November 2012, Copenhagen, Denmark
Available from: 2012-10-04 Created: 2012-10-04 Last updated: 2015-11-26Bibliographically approved
##### In thesis
1. Building Blocks for Low-Voltage Analog-to-Digital Interfaces
Open this publication in new window or tab >>Building Blocks for Low-Voltage Analog-to-Digital Interfaces
2014 (English)Licentiate thesis, comprehensive summary (Other academic)
##### Abstract [en]

In today’s system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.

To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/$\small\sqrt{Hz}$ while consuming 6.8 mW.

Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain  frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.

Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium resolution. The generation and buffering of reference voltages is often not the focus of published works. For high-speed SAR ADCs, due to the sequential nature of the successive approximation algorithm, a high-frequency clock for the SAR logic is needed. As the digital-to-analog converter (DAC) output voltage needs to settle to the desired accuracy within half clock cycle period of the system clock, a speed limitation occurs due to imprecise DAC settling. The situation is exacerbated by parasitic inductance of bondwires and printed circuit board (PCB) traces especially when the reference voltages are supplied off-chip. In this thesis, a power efficient reference voltage buffer with small area has been implemented in 180 nm CMOS for a 10-bit 1 MS/s SAR ADC which is intended to be used in a fingerprint sensor. Since the reference voltage buffer is part of an industrial SoC, critical performance specifications such as fast settling, high power supply rejection ratio (PSRR), and low noise have to be satisfied under mismatch conditions and over the entire range of process, supply voltage and temperature (PVT) corners. A single-ended, current-mirror amplifier with cascodes has been designed to buffer the reference voltage. Performance of the buffer has been verified by exhaustive simulations on the post-layout extracted netlist.

Finally, we describe the design of a 10-bit 50 MS/s SAR ADC in 65 nmCMOS with a high-speed, on-chip reference voltage buffer. In a SAR ADC, the capacitive array DAC is the most area-intensive block. Also a binary-weighted capacitor array has a large spread of capacitor values for moderate and high resolutions which leads to increased power consumption. In this work, a split binary-weighted capacitive array DAC has been used to reduce area and power consumption. The proposed ADC has bootstrapped sampling switches which meet 10-bit linearity over all PVT corners and a two-stage dynamic comparator. The important design parameters of the reference voltage buffer are derived in the context of the SAR ADC. The impact of the buffer on the ADC performance is illustrated by simulations using bondwire parasitics. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner, and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

##### Series
Linköping Studies in Science and Technology. Thesis, ISSN 0280-7971 ; 1666
##### National Category
Electrical Engineering, Electronic Engineering, Information Engineering
##### Identifiers
urn:nbn:se:liu:diva-111958 (URN)10.3384/lic.diva-111958 (DOI)978-91-7519-302-1 (ISBN)
##### Presentation
2014-09-05, Visionen, Hus B, Campus Valla, Linköpings universitet, 10:15 (English)
##### Supervisors
Available from: 2014-11-11 Created: 2014-11-11 Last updated: 2014-11-11Bibliographically approved
2. Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces
Open this publication in new window or tab >>Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
##### Abstract [en]

The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At VDD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm2.

The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-to-high sampling rates, the DAC reference settling poses a speed bottleneck in charge-redistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 μW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.

The third contribution comprises five disparate works involving the design of key peripheral blocks of the ADC such as reference voltage buffer and programmable gain amplifier (PGA) as well as low-voltage, multi-stage OTAs. These works are a) Design of a 1 V, fully differential OTA which satisfies the demanding specifications of a PGA for a 9-bit SAR ADC in 28 nm UTBB FDSOI CMOS. While consuming 2.9 μW, the PGA meets the various performance specifications over all process corners and a temperature range of [−20◦ C +85◦ C]. b) Since FBB in the 28 nm FDSOI process allows wide tuning of the threshold voltage and substantial boosting of the transconductance, an ultra-low-voltage fully differential OTA with VDD = 0.4 V has been designed to satisfy the comprehensive specifications of a general-purpose OTA while limiting the power consumption to 785 nW. c) Design and implementation of a power-efficient reference voltage buffer in 1.8 V, 180 nm CMOS for a 10-bit, 1 MS/s SAR ADC in an industrial fingerprint sensor SoC. d) Comparison of two previously-published frequency compensation schemes on the basis of unity-gain frequency and phase margin on a three-stage OTA designed in a 1.1 V, 40-nm CMOS process. Simulation results highlight the benefits of split-length indirect compensation over the nested Miller compensation scheme. e) Design of an analog front-end (AFE) satisfying the requirements for a capacitive body-coupled communication receiver in a 1.1 V, 40-nm CMOS process. The AFE consists of a cascade of three amplifiers followed by a Schmitt trigger and digital buffers. Each amplifier utilizes a two-stage OTA with split-length compensation.

##### Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1728
##### National Category
Signal Processing Electrical Engineering, Electronic Engineering, Information Engineering
##### Identifiers
urn:nbn:se:liu:diva-122730 (URN)10.3384/diss.diva-122730 (DOI)978-91-7685-890-5 (ISBN)
##### Public defence
2016-01-22, Visionen, B-huset, Campus Valla, Linköping, 13:15 (English)
##### Supervisors
Available from: 2015-11-18 Created: 2015-11-18 Last updated: 2015-12-11Bibliographically approved
3. Variation-Aware System Design Simulation Methodology for Capacitive BCC Transceivers
Open this publication in new window or tab >>Variation-Aware System Design Simulation Methodology for Capacitive BCC Transceivers
2015 (English)Doctoral thesis, comprehensive summary (Other academic)
##### Abstract [en]

Capacitive body coupled communication (BCC), frequency range 500 kHz to 15 MHz, is considered an emerging alternate short range wireless technology which can meet the stringent low power consumption (< 1 mW) and low data rate (< 100 kbps) requirements for the next generation of connected devices for applications like internet-of-things (IoT) and wireless sensor network (WSN). But a reliable solution for this mode of communication covering all possible body positions and maximum communication distances around the human body could not be presented so far, despite its inception around 20 years back in 1995. The uncertainties/errors associated with experimental measurement setup create ambiguity about the measured propagation loss or transmission errors. The reason is the usage of either earth grounded lab instruments or the direct coupling of earth ground with transmitter/receiver or the analog front end cut-off frequency limitations in a few MHz region or the balun to provide isolation or the measurements on simplified homogeneous biological phantoms. Another source of ambiguity in the experimental measurements is attributed to the natural variations in human tissue electrophysiological properties from person to person which are also affected by physical factors like age, gender, number of cells at different body locations and humidity. The analytical models presented in the literature are also oversimplified which do not predict the true propagation loss for capacitive BCC channel.

An attempt is being made to understand and demonstrate, qualitatively and quantitatively, the physical phenomenon of signal transmission and propagation characteristics e.g., path loss in complex scenarios for capacitive BCC channel by both the experimental observations/measurements and simulation models in this PhD dissertation. An alternate system design simulation methodology has been proposed which estimates the realistic path loss even for longer communication distances > 50 cm for capacitive BCC channel. The proposed simulation methodology allows to vary human tissue dielectric/thickness properties and easily integrates with the circuit simulators as the output is in the form of S-parameters. The advantage is that the capacitive BCC channel characteristics e.g., signal attenuation as a function of different physical factors could be readily simulated at the circuit level to choose appropriate circuit topology and define suitable system specifications. This simulation methodology is based on full-wave electromagnetic analysis and 3D modeling of human body and environment using their conductivity, permittivity, and tangent loss profile to estimate the realistic propagation loss or path loss due to their combined interaction with the electrode coupler for capacitive BCC channel. This methodology estimates the complex path impedance from transmitter to receiver which is important to determine the matching requirements for maximum power transfer. The simulation methodology also contributes towards better understanding of signal propagation through physical channel under the influence of different electrode coupler configurations. The simulation methodology allows to define error bounds for variations in propagation loss due to both numeric uncertainties (boundary conditions, mesh cells) and human body variation uncertainties (dielectric properties, dielectric thicknesses) for varying communication distances and coupler configuration/sizes.

Besides proposing the simulation methodology, the digital baseband and passband communication architectures using discrete electronics components have been experimentally demonstrated in the context of IoT application through capacitive BCC channel for data rates between 1 kbps to 100 kbps under isolated earth ground conditions. The experimental results/observations are supported by the simulation results for different scenarios of capacitive BCC channel.

The experimental and simulation results help in defining suitable system specifications for monolithic integrated circuit design of analog front end (AFE) blocks for capacitive BCC transmitter/receiver in deep submicron CMOS technologies.

##### Series
Linköping Studies in Science and Technology. Dissertations, ISSN 0345-7524 ; 1721
##### National Category
Electrical Engineering, Electronic Engineering, Information Engineering Computer Sciences
##### Identifiers
urn:nbn:se:liu:diva-122840 (URN)10.3384/diss.diva-122840 (DOI)978-91-7685-906-3 (ISBN)
##### Public defence
2015-12-18, Visionen, Hus B, Campus Valla, Linköping, 13:15 (English)
##### Note

The series name Linköping Studies in Science and Technology. Thesis in the printed version is incorrect. The correct name is Linköping Studies in Science and Technology. Dissertations. This is corrected in the electronic version.

In the electronic published version minor errors in the acknowledgements and some typographical mistakes has been corrected.

Available from: 2015-11-26 Created: 2015-11-26 Last updated: 2018-01-10Bibliographically approved

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Cite
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