A Process Variation Tolerant DLL-Based UWB Frequency Synthesizer
2012 (English)In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), IEEE , 2012, 558-561 p.Conference paper (Refereed)
A calibration technique for compensation of the generated phase error at the band hopping instant is proposed for a fast-hopping DLL-based injection-locked frequency synthesizer for WiMedia UWB band group #1. This technique makes the accuracy of the phase error compensation immune to process variations and so the VCDL nonlinearity. Simulated in 65-nm CMOS technology, the average synthesizer hopping time is 4 ns for all process corners. The phase noise performance at 1 MHz offset from 4488 MHz carrier is -121 dBc/Hz and the adjacent spur level from the Monte Carlo simulation is -37 dBc. Excluding the CML divider, the synthesizer consumes 7.7 mW from a 1.2 V supply.
Place, publisher, year, edition, pages
IEEE , 2012. 558-561 p.
, Midwest Symposium on Circuits and Systems. Conference Proceedings, ISSN 1548-3746 ; 2012
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-86344DOI: 10.1109/MWSCAS.2012.6292081ISI: 000312667200140ISBN: 978-1-4673-2525-7 (online)ISBN: 978-1-4673-2526-4 (print)OAI: oai:DiVA.org:liu-86344DiVA: diva2:576620
55th IEEE International Midwest Symposium on Circuits and systems (MWSCAS 2012), 5-8 August 2012, Boise, Idaho, USA