A 3-nW 9.1-ENOB SAR ADC at 0.7 V and 1 kS/s
2012 (English)In: ESSCIRC, 2012, Institute of Electrical and Electronics Engineers , 2012, 369-372 p.Conference paper (Refereed)
This paper presents a 10-bit SAR ADC in 65 nm CMOS for medical implant applications. The ADC consumes 3-nW power and achieves 9.1 ENOB at 1 kS/s. The ultra-low-power consumption is achieved by using an ADC architecture with maximal simplicity, a small split-array capacitive DAC, a bottom-plate sampling approach reducing charge injection error and allowing full-range input sampling without extra voltage sources, and a latch-based SAR control logic resulting in reduced power and low transistor count. Furthermore, a multi-Vt circuit design approach allows the ADC to meet the target performance with a single supply voltage of 0.7 V. The ADC achieves a FOM of 5.5 fJ/conversion-step. The INL and DNL errors are 0.61 LSB and 0.55 LSB, respectively.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers , 2012. 369-372 p.
, IEEEESSCIRC Proceedings, ISSN 1930-8833
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:liu:diva-86346DOI: 10.1109/ESSCIRC.2012.6341331ISBN: 978-1-4673-2211-9 (online)ISBN: 978-1-4673-2212-6 (print)OAI: oai:DiVA.org:liu-86346DiVA: diva2:576627
IEEE European Solid-State Circuits Conference (ESSCIRC 2012), 17-21 September 2012, Bordeaux, France