Analog MAC unit with digital coefficients suitable for IF filtering and demodulation
(English)Manuscript (preprint) (Other academic)
A digitally programmable analog interface for communication applications is presented. The interface consists of a sampler, an analog multiplier, and an analog accumulator; where the analog multiplier features signed 8-bit coefficient resolution. The interface is implemented with switched-capacitor technique and is demonstrated with a test chip, fabricated using a low-cost 0.6)μm CMOS process.The interface is shown to be able to combine a programmable band-pass filter of FIR type with a demodulator for quadrature modulation. The bandwidth and center frequency of this filter is programmable with a fixed clock frequency, which is a useful property in multi-standard receivers. As a demonstration, the interface is controlled, in real-time by digital control stimuli, to act as sampler and combined 27th-order FIR filter and demodulator at three different frequencies; 1.43MHz, 2.50MHz, and 3.57MHz. The test chip clock frequency is fixed to 10MHz. The test chip hence samples, filters, and demodulates a 357kSymbol/s QPSK modulated waveform with carrier frequency 1.43MHz, 2.50MHz, or 3.57MHz, and with power -61dBm. The measured ultimate rejection of the 27th-order FIR filter is measured to 25dB, and the noise figure is measured to 29dB.
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-86797OAI: oai:DiVA.org:liu-86797DiVA: diva2:582402