Defect structures at the silicon/3C-SiC interface
2012 (English)In: Materials Science Forum Vols 717 - 720, Trans Tech Publications Inc., 2012, Vol. 717-720, 423-426 p.Conference paper (Refereed)
In all heteroepitaxial systems the interface between substrate and layer is a crucial point. In this work SEM and TEM studies on the interface between silicon substrate and cubic silicon carbide (3C-SiC) layers obtained by chemical vapor deposition (CVD) are presented. A clear connection between process parameters, like the design of substrate cleaning, and the heating ramp, and resulting defect structures at the substrate-layer interface could be found. Whereas the process step of etching in hot hydrogen for oxide removal is crucial for avoiding the generation of closed voids of type 2, the design of the temperature ramp-up to growth temperature during carbonization influences the interface roughness. Here a fast ramp helps to obtain a flat interface.
Place, publisher, year, edition, pages
Trans Tech Publications Inc., 2012. Vol. 717-720, 423-426 p.
cubic silicon carbide; heteroepitaxy; interface; dislocations; roughness; voids
Engineering and Technology
IdentifiersURN: urn:nbn:se:liu:diva-87576DOI: 10.4028/www.scientific.net/MSF.717-720.423ISI: 000309431000100OAI: oai:DiVA.org:liu-87576DiVA: diva2:589556
14th International Conference on Silicon Carbide and Related Materials (ICSCRM 2011), 11-16 September 2011, Cleveland, OH, USA